[XS] Change in coreboot[main]: mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPU

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84278?usp=email )

Change subject: mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPU
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mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPU

Check that lnkCap supports ASPM L1, so set it to ASPM_L1
to avoid excessive power consumption.

BUG=b:363854853
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Change-Id: I386f8e88a5af661b1f4c04d2e2a34cd181608bd8
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84278
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: 
---
M src/mainboard/google/brox/variants/brox/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  [e-mail]: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index f2342f0..79771eb 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -273,6 +273,7 @@
    			.clk_req = 3,
    			.clk_src = 3,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1
    		}"
    		probe STORAGE STORAGE_NVME
    		probe unprovisioned