Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61458 )
Change subject: soc/intel/alderlake: Choose PMC IPC to disable HECI1 ......................................................................
soc/intel/alderlake: Choose PMC IPC to disable HECI1
This patch allows common CSE block to make HECI1 function disable using PMC IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config on alderlake to perform heci1 disabling using PMC IPC.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/smihandler.c 2 files changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61458/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 04e113a..1616029 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -76,6 +76,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 61fecdf..56814f5 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -16,9 +16,6 @@ */ void smihandler_soc_at_finalize(void) { - if (!CONFIG(HECI_DISABLE_USING_SMM)) - return; - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); }