Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59392 )

Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2
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mb/intel/adlrvp: Enable CPU PCIe RP 2

Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.

Signed-off-by: Meera Ravindranath 
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 8926887..2c45e85 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -83,6 +83,12 @@
    	.clk_src = 0,
    }"

+	# Enable CPU PCIE RP 2 using CLK 3
+	register "cpu_pcie_rp[CPU_RP(2)]" = "{
+		.clk_req = 3,
+		.clk_src = 3,
+	}"
+
    # Enable CPU PCIE RP 3 using CLK 4
    register "cpu_pcie_rp[CPU_RP(3)]" = "{
    	.clk_req = 4,