Change in coreboot[master]: Spell Intel Cooper Lake-SP with a space

[Paul Menzel (Code Review)]

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59036 )

Change subject: Spell Intel Cooper Lake-SP with a space
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Spell Intel Cooper Lake-SP with a space

Use the official spelling. [1]

[1]: https://ark.intel.com/content/www/us/en/ark/products/codename/189143/product...

Change-Id: I7dbd332600caa7c04fc4f6bac53880e832e97bda
Signed-off-by: Paul Menzel 
---
M Documentation/releases/coreboot-4.14-relnotes.md
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/cpx/chip.c
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/59036/1

diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
index 40589a1..4f2b00e 100644
--- a/Documentation/releases/coreboot-4.14-relnotes.md
+++ b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -142,7 +142,7 @@

coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
 This release has support for SkyLake-SP (SKX-SP) which is the 2nd
-generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
+generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation
 or the latest generation [2] on market.

With this release, the codebase for multiple generations of Xeon-SP
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index fa8403a..965d5da 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -20,7 +20,7 @@
    select PLATFORM_USES_FSP2_2
    select CACHE_MRC_SETTINGS
    help
-	  Intel Cooperlake-SP support
+	  Intel Cooper Lake-SP support

if XEON_SP_COMMON_BASE

diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 19bf2af..a4da344 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -186,7 +186,7 @@
 }

struct chip_operations soc_intel_xeon_sp_cpx_ops = {
-	CHIP_NAME("Intel Cooperlake-SP")
+	CHIP_NAME("Intel Cooper Lake-SP")
    .enable_dev = chip_enable_dev,
    .init = chip_init,
    .final = chip_final,