Change in coreboot[master]: nb/amd/agesa/family14: Enable PARALLEL_MP

[Arthur Heymans (Code Review)]

Attention is currently required from: Michał Żygowski, Michał Kopeć, Paul Menzel.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59807 )

Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP
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Patch Set 16:

(3 comments)

File src/cpu/amd/agesa/family14/model_14_init.c:

https://review.coreboot.org/c/coreboot/+/59807/comment/2fb26800_a4dcc271 
PS16, Line 22: enable_cache();
also done by the SIPI stub so remove.

File src/northbridge/amd/agesa/family14/northbridge.c:

https://review.coreboot.org/c/coreboot/+/59807/comment/7df7f8bd_2760b4e5 
PS16, Line 311: if (acpi_is_wakeup_s3())
              : 		restore_mtrr();
              : 	else
remove.

https://review.coreboot.org/c/coreboot/+/59807/comment/b94c747a_57efe9dd 
PS16, Line 321: uint8_t siblings = cpuid_ecx(0x80000008) & 0xff;
              : 
              : 	return siblings + 1;
Should this change? It looks like most other AMD code does read this from the PCI config space.