New subject: Change in coreboot[master]: mb/google/volteer: Create lindar variant

21 Jul 2020

Julia Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43671 )
Change subject: mb/google/volteer:Createlindarvariant
......................................................................
mb/google/volteer:Createlindarvariant
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com
Change-Id: Ibfe10b2caa6ea3b664a22f5a3dad187d3f9d0f2a
---
M src/mainboard/google/volteer/Kconfig
M src/mainboard/google/volteer/Kconfig.name
A src/mainboard/google/volteer/variants/lindar/Makefile.inc
A src/mainboard/google/volteer/variants/lindar/gpio.c
A src/mainboard/google/volteer/variants/lindar/include/variant/ec.h
A src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h
A src/mainboard/google/volteer/variants/lindar/memory.c
A src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc
A src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt
A src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt
A src/mainboard/google/volteer/variants/lindar/overridetree.cb
11 files changed, 422 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/43671/1

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index 16834ae..4056a23 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -75,6 +75,7 @@
    default "Volteer2" if BOARD_GOOGLE_VOLTEER2
    default "Voxel" if BOARD_GOOGLE_VOXEL
    default "Delbin" if BOARD_GOOGLE_DELBIN
+        default "Lindar" if BOARD_GOOGLE_LINDAR
config MAX_CPUS
    int
@@ -108,6 +109,7 @@
    default "volteer2" if BOARD_GOOGLE_VOLTEER2
    default "voxel" if BOARD_GOOGLE_VOXEL
    default "delbin" if BOARD_GOOGLE_DELBIN
+        default "lindar" if BOARD_GOOGLE_LINDAR
config VARIANT_HAS_MIPI_CAMERA
    bool
diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name
index 06bbc58..ef3f5d0 100644
--- a/src/mainboard/google/volteer/Kconfig.name
+++ b/src/mainboard/google/volteer/Kconfig.name
@@ -42,3 +42,7 @@
    bool "-> Delbin"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
+config BOARD_GOOGLE_LINDAR
+        bool "-> Lindar"
+        select BOARD_GOOGLE_BASEBOARD_VOLTEER
+        select SOC_INTEL_CSE_LITE_SKU
diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc
new file mode 100644
index 0000000..343c7db
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c
new file mode 100644
index 0000000..cdffb60
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/gpio.c
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+	/* A0 thru A6 come configured out of reset, do not touch */
+	/* A0  : ESPI_IO0 ==> ESPI_IO_0 */
+	/* A1  : ESPI_IO1 ==> ESPI_IO_1 */
+	/* A2  : ESPI_IO2 ==> ESPI_IO_2 */
+	/* A3  : ESPI_IO3 ==> ESPI_IO_3 */
+	/* A4  : ESPI_CS# ==> ESPI_CS_L */
+	/* A5  : ESPI_CLK ==> ESPI_CLK */
+	/* A6  : ESPI_RESET# ==> NC(TP764) */
+	/* A7  : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
+	PAD_CFG_GPO(GPP_A7, 1, DEEP),
+	/* A8  : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
+	PAD_CFG_GPO(GPP_A8, 0, DEEP),
+	/* A10 : I2S2_RXD ==> EN_SPKR_PA */
+	PAD_CFG_GPO(GPP_A10, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
+	/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A18 : DDSP_HPDB ==> HDMI_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+	/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+	/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
+	/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
+	PAD_CFG_GPO(GPP_A22, 1, DEEP),
+	/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+
+	/* B2  : VRALERT# ==> NOT USED */
+	PAD_NC(GPP_B2, NONE),
+	/* B3  : CPU_GP2 ==> PEN_DET_ODL */
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+	/* B9  : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+	/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+	/* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+
+	/* C0  : SMBCLK ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C7  : SML1DATA ==> EN_USI_CHARGE */
+	PAD_CFG_GPO(GPP_C7, 1, DEEP),
+	/* C10 : UART0_RTS# ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	/* C11 : UART0_CTS# ==> NOT USED */
+	PAD_NC(GPP_C11, NONE),
+	/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* C20 : UART2_RXD ==> FPMCU_INT_L */
+	PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
+	/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+	/* D5  : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D6  : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
+	/* D17 : ISH_GP4 ==> EN_CVF_PWR */
+	PAD_CFG_GPO(GPP_D17, 1, DEEP),
+
+	/* E1  : SPI1_IO2 ==> PEN_DET_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+	/* E2  : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	/* E3  : CPU_GP0 ==> USI_REPORT_EN */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
+	/* E4  : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+	/* E7  : CPU_GP1 ==> USI_INT */
+	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+	/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+	/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
+	PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+	/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+
+	/* F6  : CNV_PA_BLANKING ==> NC */
+	PAD_NC(GPP_F6, NONE),
+	/* F8  : I2S_MCLK2_INOUT ==> HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
+	/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
+	PAD_CFG_GPO(GPP_F13, 1, DEEP),
+	/* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
+	PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+
+	/* H3  : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H3, 1, DEEP),
+	/* H8  : I2C4_SDA ==> NC */
+	PAD_NC(GPP_H8, NONE),
+	/* H9  : I2C4_SCL ==> NC */
+	PAD_NC(GPP_H9, NONE),
+	/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H11, 1, DEEP),
+	/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+	/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */
+	PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+
+	/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+	/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+	/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+	/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+	/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+
+	/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+
+	/* B11 : PMCALERT# ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+
+	/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+
+	/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+
+	/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+
+	/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+
+	/* C0  : SMBCLK ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+
+	/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+
+	/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+	/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
+	PAD_CFG_GPO(GPP_E12, 1, DEEP),
+
+	/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H11, 1, DEEP),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h b/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h
new file mode 100644
index 0000000..4a9a461
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h b/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h
new file mode 100644
index 0000000..0075826
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+/* Copied from baseboard and may need to change for the new variant. */
+
+#endif
diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c
new file mode 100644
index 0000000..ea81216
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/memory.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+
+static const struct lpddr4x_cfg lindar_memcfg = {
+	/* DQ byte map */
+	.dq_map = {
+		[0] = {
+			{ 3,  1,  0,  2,  4,  6,  7,  5, }, /* DDR0_DQ0[7:0] */
+			{ 12, 13, 14, 15,  8,  9, 10, 11 }, /* DDR0_DQ1[7:0] */
+		},
+		[1] = {
+			{ 0,  7,  1,  6,  2,  4,  3,  5, }, /* DDR1_DQ0[7:0] */
+			{ 8,  15, 14,  9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */
+		},
+		[2] = {
+			{ 3,  2,  0,  1,  4,  5,  6,  7, }, /* DDR2_DQ0[7:0] */
+			{ 12, 13, 15, 14,  8,  9, 10, 11 }, /* DDR2_DQ1[7:0] */
+		},
+		[3] = {
+			{ 6,  0,  1,  7,  5,  4,  2,  3, }, /* DDR3_DQ0[7:0] */
+			{ 15, 14,  8,  9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */
+		},
+		[4] = {
+			{ 5,  0,  1,  3,  4,  2,  7,  6, }, /* DDR4_DQ0[7:0] */
+			{ 11, 14, 13, 12,  8,  9, 15, 10 }, /* DDR4_DQ1[7:0] */
+		},
+		[5] = {
+			{  3,  4,  2,  5,  0,  6,  1,  7, }, /* DDR5_DQ0[7:0] */
+			{  13, 12, 11, 10, 14, 15,  9,  8 }, /* DDR5_DQ1[7:0] */
+		},
+		[6] = {
+			{  3,  2,  1,  0,  5,  4,  7,  6, }, /* DDR6_DQ0[7:0] */
+			{  12, 13, 15, 14,  8, 11,  9, 10 }, /* DDR6_DQ1[7:0] */
+		},
+		[7] = {
+			{  3,  4,  2,  5,  1,  0,  7,  6, }, /* DDR7_DQ0[7:0] */
+			{  15, 14,  9,  8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+		[0] = { 0, 1 },  /* DDR0_DQS[1:0] */
+		[1] = { 0, 1 },  /* DDR1_DQS[1:0] */
+		[2] = { 0, 1 },  /* DDR2_DQS[1:0] */
+		[3] = { 0, 1 },  /* DDR3_DQS[1:0] */
+		[4] = { 0, 1 },  /* DDR4_DQS[1:0] */
+		[5] = { 0, 1 },  /* DDR5_DQS[1:0] */
+		[6] = { 0, 1 },  /* DDR6_DQS[1:0] */
+		[7] = { 0, 1 },  /* DDR7_DQS[1:0] */
+	},
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+const struct lpddr4x_cfg *variant_memory_params(void)
+{
+	return &lindar_memcfg;
+}
diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc
new file mode 100644
index 0000000..4c95819
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+
+SPD_SOURCES =
+SPD_SOURCES += spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AA-MGCL
diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt
new file mode 100644
index 0000000..9bf0bd9
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt
@@ -0,0 +1,2 @@
+DRAM Part Name                 ID to assign
+K4U6E3S4AA-MGCL                0 (0000)
diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt
new file mode 100644
index 0000000..a226d2f
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt
@@ -0,0 +1 @@
+K4U6E3S4AA-MGCL
diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
new file mode 100644
index 0000000..c84ed83
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
@@ -0,0 +1,120 @@
+chip soc/intel/tigerlake
+
+	# USB Port Config
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C C1
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C C0
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
+
+	register "SaGv" = "SaGv_Disabled"
+
+	# I2C Port Config
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	device domain 0 on
+		device pci 07.0 off end # TBT_PCIe0			0x9A23
+		device pci 07.1 off end # TBT_PCIe1			0x9A25
+		device pci 07.2 off end # TBT_PCIe2			0x9A27
+		device pci 07.3 off end # TBT_PCIe3			0x9A29
+		device pci 15.0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end # I2C0
+		device pci 15.1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+				register "generic.reset_delay_ms" = "120"
+				register "generic.reset_off_delay_ms" = "3"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 5d on end
+			end
+		end # I2C1
+		device pci 15.2 on
+			chip drivers/i2c/sx9310
+				register "desc" = ""SAR0 Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "0"
+				register "reg_prox_ctrl0" = "0x10"
+				register "reg_prox_ctrl1" = "0x00"
+				register "reg_prox_ctrl2" = "0x84"
+				register "reg_prox_ctrl3" = "0x0e"
+				register "reg_prox_ctrl4" = "0x07"
+				register "reg_prox_ctrl5" = "0xc6"
+				register "reg_prox_ctrl6" = "0x20"
+				register "reg_prox_ctrl7" = "0x0d"
+				register "reg_prox_ctrl8" = "0x8d"
+				register "reg_prox_ctrl9" = "0x43"
+				register "reg_prox_ctrl10" = "0x1f"
+				register "reg_prox_ctrl11" = "0x00"
+				register "reg_prox_ctrl12" = "0x00"
+				register "reg_prox_ctrl13" = "0x00"
+				register "reg_prox_ctrl14" = "0x00"
+				register "reg_prox_ctrl15" = "0x00"
+				register "reg_prox_ctrl16" = "0x00"
+				register "reg_prox_ctrl17" = "0x00"
+				register "reg_prox_ctrl18" = "0x00"
+				register "reg_prox_ctrl19" = "0x00"
+				register "reg_sar_ctrl0" = "0x50"
+				register "reg_sar_ctrl1" = "0x8a"
+				register "reg_sar_ctrl2" = "0x3c"
+				device i2c 28 on end
+			end
+		end # I2C2				0xA0EA
+		device pci 19.1 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end # I2C5				0xA0C6
+		device pci 1f.3 on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98357A""
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
+				register "sdmode_delay" = "5"
+				device generic 0 on end
+			end
+		end # Intel HD audio
+	end
+end
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibfe10b2caa6ea3b664a22f5a3dad187d3f9d0f2a
Gerrit-Change-Number: 43671
Gerrit-PatchSet: 1
Gerrit-Owner: Julia Tsai julia.tsai@lcfc.corp-partner.google.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: mb/google/volteer:Createlindarvariant