Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31785
Change subject: soc/intel/braswell: Use IRQ 9 for SCI ......................................................................
soc/intel/braswell: Use IRQ 9 for SCI
Default reserved value of used for SCI IRQ. Configure SCIS field to use IRQ 9.
BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I09aca433528b6f64ad3ff3753ae8392c0d89cdc0 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/soc/intel/braswell/southcluster.c 1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31785/1
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 22fe853..7b5dad0 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -4,7 +4,7 @@ * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -264,6 +264,7 @@ int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const unsigned long ilb_base = ILB_BASE_ADDRESS; void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); const struct soc_irq_route *ir = &global_soc_irq_route; struct soc_intel_braswell_config *config = dev->chip_info; @@ -271,6 +272,14 @@ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
+ /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + + /* Use IRQ9 for SCI Interrupt */ + write32((void *)(ilb_base + ACTL), 0); + isa_dma_init();
/* Set up the PIRQ PIC routing based on static config. */
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31785 )
Change subject: soc/intel/braswell: Use IRQ 9 for SCI ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31785/1/src/soc/intel/braswell/southcluster.... File src/soc/intel/braswell/southcluster.c:
https://review.coreboot.org/#/c/31785/1/src/soc/intel/braswell/southcluster.... PS1, Line 281: write32((void *)(ilb_base + ACTL), 0); This is the leftover from IO APIC initializaiton? Everythig else is already set by FSP?
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31785 )
Change subject: soc/intel/braswell: Use IRQ 9 for SCI ......................................................................
Patch Set 1:
(1 comment)
SCI interrupt number must be configured.
https://review.coreboot.org/#/c/31785/1/src/soc/intel/braswell/southcluster.... File src/soc/intel/braswell/southcluster.c:
https://review.coreboot.org/#/c/31785/1/src/soc/intel/braswell/southcluster.... PS1, Line 281: write32((void *)(ilb_base + ACTL), 0);
This is the leftover from IO APIC initializaiton? Everythig else is already set by FSP?
Yes, FSP does not configure SCI interrupt.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31785 )
Change subject: soc/intel/braswell: Use IRQ 9 for SCI ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31785 )
Change subject: soc/intel/braswell: Use IRQ 9 for SCI ......................................................................
soc/intel/braswell: Use IRQ 9 for SCI
Default reserved value of used for SCI IRQ. Configure SCIS field to use IRQ 9.
BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I09aca433528b6f64ad3ff3753ae8392c0d89cdc0 Signed-off-by: Frans Hendriks fhendriks@eltan.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31785 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/soc/intel/braswell/southcluster.c 1 file changed, 10 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index b8263db..e79cb12 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -4,7 +4,7 @@ * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -267,6 +267,7 @@ int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const unsigned long ilb_base = ILB_BASE_ADDRESS; void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); const struct soc_irq_route *ir = &global_soc_irq_route; struct soc_intel_braswell_config *config = dev->chip_info; @@ -274,6 +275,14 @@ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
+ /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + + /* Use IRQ9 for SCI Interrupt */ + write32((void *)(ilb_base + ACTL), 0); + isa_dma_init();
/* Set up the PIRQ PIC routing based on static config. */
-
Frans Hendriks (Code Review) -
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)