Change in coreboot[master]: soc/intel/tigerlake: Update GPIOs for Tigerlake SOC

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36248 )

Change subject: soc/intel/tigerlake: Update GPIOs for Tigerlake SOC
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Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/36248/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36248/3//COMMIT_MSG@30 
PS3, Line 30: BUG=None
> Please stop talking nonsense.

please be reasonable while writing "stop talking nonsense" like sentences.
this is a copy patch from ICL hence you are seeing offset 0x20 changes to offset 0x40 (which i still have doubt that it shouldn't be), but if yes, then this are early sets of patch to establish TGL code base and TGL platfrom in open source. i really don't understand what you mean "TGL commit is technically broken."?
> If the register offset is completly different, then the TGL commit is technically broken.

Answered above

https://review.coreboot.org/c/coreboot/+/36248/3//COMMIT_MSG@32 
PS3, Line 32: TEST=None
> How you know it doesn't ... […]

i have asked submitted to write test to know till what stage we have booted and how do we verify.