[XS] Change in coreboot[main]: soc/intel/ptl: Enable UFS functionality by adding IRQ programming

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85536?usp=email )

Change subject: soc/intel/ptl: Enable UFS functionality by adding IRQ programming
......................................................................

soc/intel/ptl: Enable UFS functionality by adding IRQ programming

This commit adds the necessary IRQ programming for the UFS controller,
addressing an issue where the device was not operational after booting
to the OS.

BUG=b:382243957
TEST=Built and booted google/fatcat successfully, verifying UFS
functionality.

with this patch

```
[SPEW ]   Interrupt assignment:
[SPEW ]    Dxx:Fx   INTx  IRQ
[SPEW ]    D23:F0    1    018
```

Change-Id: Ib479f0adaaae64cee4d2152534dae40e32614065
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85536
Reviewed-by: Kapil Porwal 
Reviewed-by: Jayvik Desai 
Reviewed-by: Divagar Mohandass 
Reviewed-by: Dinesh Gehlot 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/pantherlake/fsp_params.c
1 file changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Divagar Mohandass: Looks good to me, but someone else must approve
  Kapil Porwal: Looks good to me, approved
  Dinesh Gehlot: Looks good to me, approved
  Jayvik Desai: Looks good to me, approved

diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index e0b0adf..dfc47c6 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -199,6 +199,14 @@
    		ANY_PIRQ(PCI_DEVFN_CSE_4),
    	},
    },
+#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+	{
+		.slot = PCI_DEV_SLOT_UFS,
+		.fns = {
+			ANY_PIRQ(PCI_DEVFN_UFS),
+		},
+	},
+#endif
    {
    	.slot = PCI_DEV_SLOT_SIO1,
    	.fns = {