Change in ...coreboot[master]: src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32310
Change subject: src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config ......................................................................
src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config
The pci_or_configx function makes the code shorter and more readable.
Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/intel/d510mo/romstage.c 2 files changed, 2 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32310/1
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index ecff4b9..cdd12dc 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -28,8 +28,7 @@ /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index c91d40e..024c3e1 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -28,8 +28,7 @@ /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32310 )
Change subject: src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32310 )
Change subject: src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config ......................................................................
Patch Set 1: Code-Review+2
I prefer syntax with pci_modify where the other related bits of COMA/COMB decode are also cleared, but I guess it's fine like this.
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32310 )
Change subject: src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config ......................................................................
src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config
The pci_or_configx function makes the code shorter and more readable.
Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/32310 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/intel/d510mo/romstage.c 2 files changed, 2 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved HAOUAS Elyes: Looks good to me, approved
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index ecff4b9..cdd12dc 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -28,8 +28,7 @@ /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index c91d40e..024c3e1 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -28,8 +28,7 @@ /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
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Arthur Heymans (Code Review) -
HAOUAS Elyes (Code Review)
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Kyösti Mälkki (Code Review)
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Patrick Georgi (Code Review)