Change in coreboot[master]: soc/intel/tigerlake: Configure Type-C IOM base address and size
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Configure Type-C IOM base address and size ......................................................................
soc/intel/tigerlake: Configure Type-C IOM base address and size
This adds Type-C IO Manageability engine base address and size. IOM register base is in offset 0x7110 from MCHBAR and its port ID is 0xc1. IOM has base address 0xfbc10000 with size 0x1600.
BUG=:b:156016218 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 --- M src/soc/intel/tigerlake/include/soc/iomap.h 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41759/1
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 282092f..cd964f0 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -84,6 +84,8 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+#define IOM_BASE_ADDRESS 0xfbc10000 +#define IOM_BASE_SIZE 0x1600
/* * I/O port address space
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Configure Type-C IOM base address and size ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG@7 PS1, Line 7: Configure Currently, only macros are added, so nothing is configured yet?
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG@12 PS1, Line 12: Please add what section in what datasheet this is described in.
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Shamile Khan, Rajmohan Mani, Patrick Rudolph, Prashant Malani, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41759
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
soc/intel/tigerlake: Add Type-C IOM base address and size macro
This adds Type-C IO Manageability engine base address and size. Tigerlake EDS(#575681) section 3.4.3 describes host bridge REGBAR(MCHBAR) + 7110h for IOM REGBAR with size up to 1600h. IOM has a port ID 0xc1. MCHBAR:0xfedc0000, IOM REGBAR:0xfb000000 from mmio (MCHBAR + 0x7110) IOM has base address 0xfbc10000 from (0xfb000000 + (0xc1 << 16)).
BUG=:b:156016218 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 --- M src/soc/intel/tigerlake/include/soc/iomap.h 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41759/2
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Shamile Khan, Rajmohan Mani, Patrick Rudolph, Prashant Malani, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41759
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
soc/intel/tigerlake: Add Type-C IOM base address and size macro
This adds Type-C IO Manageability engine base address and size. Tigerlake EDS(#575681) section 3.4.3 describes host bridge REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000. IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).
BUG=:b:156016218 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 --- M src/soc/intel/tigerlake/include/soc/iomap.h 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41759/3
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG@7 PS1, Line 7: Configure
Currently, only macros are added, so nothing is configured yet?
Updated as "Add Type-C IOM base address and size macro".
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG@12 PS1, Line 12:
Please add what section in what datasheet this is described in.
Updated the description by adding EDS(#575681) and IOM base address determination.
Rajmohan Mani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG@9 PS1, Line 9: IO Manageability engine Input Output Manager (IOM) device
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG@13 PS1, Line 13: : Remove?
Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41759/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41759/3//COMMIT_MSG@17 PS3, Line 17: EST=Built and booted on Volteer. Hi John,
Can we have more directed testing here? We've run into an issue recently where some TBT patches had "Built and booted on Volteer" as their test string, but broke TBT.
Please test this with an internal version of the IOM driver (along with either extcon or the cros-ec-typec patches I provided), so that we have confidence that the following still work:
- USB4/TBT enumeration - DP + USB3 alternate mode. - USB SuperSpeed thumb drive enumeration.
The above should still work for the following configurations: - Both Type C ports - Both cable orientations.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41759/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41759/3//COMMIT_MSG@17 PS3, Line 17: EST=Built and booted on Volteer.
Hi John, […]
Hi Prashant, as you might know that issue was due to dependency TBT patches were not merged. We do testing before submitting patch. This patch along with CB:41762 is intended to be used by IOM driver which is still under development and review. I will mark this patch to be WIP.
Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3:
(1 comment)
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41759/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41759/3//COMMIT_MSG@17 PS3, Line 17: EST=Built and booted on Volteer.
Hi Prashant, as you might know that issue was due to dependency TBT patches were not merged. […]
Thanks. When you are ready to move this patch out of WIP, please do update the TEST string with the tests that you have run. This helps our engineers when we're diagnosing failures, and also helps folks with less context about this domain determine whether the patch has had a decent level of testing.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3:
(1 comment)
Sure, we will update the test string.
https://review.coreboot.org/c/coreboot/+/41759/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41759/3//COMMIT_MSG@17 PS3, Line 17: EST=Built and booted on Volteer.
Thanks. […]
Sure, will update the test string.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3: Code-Review-1
Do not merge. To be along with kernel Input Output Manager driver.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3: Code-Review+1
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3:
Patch Set 3: Code-Review-1
Do not merge. To be along with kernel Input Output Manager driver.
Verified with internal version of IOM driver and extcon driver that the IOM driver gets probed and is able to read the IOM_PORT_STATUS register successfully.
Rajmohan Mani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 3: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 4: Code-Review+2
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG@9 PS1, Line 9: IO Manageability engine
Input Output Manager (IOM) device
Done
https://review.coreboot.org/c/coreboot/+/41759/1//COMMIT_MSG@13 PS1, Line 13: :
Remove?
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
soc/intel/tigerlake: Add Type-C IOM base address and size macro
This adds Type-C IO Manageability engine base address and size. Tigerlake EDS(#575681) section 3.4.3 describes host bridge REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000. IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).
BUG=:b:156016218 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Rajmohan Mani rajmohan.mani@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/include/soc/iomap.h 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Rajmohan Mani: Looks good to me, but someone else must approve John Zhao: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 282092f..cd964f0 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -84,6 +84,8 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+#define IOM_BASE_ADDRESS 0xfbc10000 +#define IOM_BASE_SIZE 0x1600
/* * I/O port address space
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John Zhao (Code Review) -
Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Prashant Malani (Code Review)
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Rajmohan Mani (Code Review)
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Tim Wawrzynczak (Code Review)
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Wonkyu Kim (Code Review)