[S] Change in coreboot[master]: [TESTONLY] Check if cacheability matters for SMM

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68816 )

Change subject: [TESTONLY] Check if cacheability matters for SMM
......................................................................

[TESTONLY] Check if cacheability matters for SMM

Change-Id: Ia0f951a9d86a6a4ffef9fc46b0307aeb1b3c6045
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/elkhartlake/finalize.c
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/68816/1

diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c
index d6ab737..c56a5ec 100644
--- a/src/soc/intel/elkhartlake/finalize.c
+++ b/src/soc/intel/elkhartlake/finalize.c
@@ -20,6 +20,7 @@
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
 #include <spi-generic.h>
+#include <cpu/x86/mtrr.h>

static void pch_finalize(void)
 {
@@ -43,6 +44,11 @@
    printk(BIOS_DEBUG, "Finalizing chipset.\n");

pch_finalize();
+
+	uintptr_t tseg_base;
+	size_t tseg_size;
+	smm_region(&tseg_base, &tseg_size);
+	mtrr_use_temp_range(tseg_base, tseg_size, MTRR_TYPE_UNCACHEABLE);
    apm_control(APM_CNT_FINALIZE);
    if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
    	 CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))