[XS] Change in coreboot[main]: soc/intel/common/block/cpu: Fix number of way computation regression

[Jérémy Compostella (Code Review)]

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Hello Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83948?usp=email

to look at the new patch set (#8).

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Verified+1 by build bot (Jenkins)

Change subject: soc/intel/common/block/cpu: Fix number of way computation regression
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soc/intel/common/block/cpu: Fix number of way computation regression

Commit 16ab9bdcd578612bb3822373547f939eb90afd82 ("soc/intel/common:
Calculate and configure SF Mask 2") breaks the computation of the
number of way and as result, all the derived masks. It results in MSR
such as `IA32_L3_MASK_1' to be improperly programmed yielding
unpredictable NEM issues such as hangs.

Indeed, this commit has introduced a backup of 0x1 into %edx before
comparing the requested cache-as-RAM size against the way size. When
the requested cache-as-RAM is larger, it reaches the second part of
the algorithm which computes the necessary number of way to fit the
requested cache-as-RAM.

This algorithm uses the `div' instruction. Per specification, the div
instruction divides the 64 bits combination of %edx and %eax register.
Since 0x1 got backed up in %edx and assuming a
`CONFIG_DCACHE_RAM_SIZE' of 0x200000, we end up dividing 0x100200000
by the way size instead of 0x200000 which result in a necessary number
of ways of 4098 for a way size of 0x100000.

This commit clears the %edx register before calling the `div'
instruction.

BUG=b:360332771
TEST=Verified on PTL Intel reference platform

Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/83948/8