New patch to review for coreboot: c4f9b1f AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8609
-gerrit
commit c4f9b1f69d168657887896c8b06f4f3e1695d901 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Thu Mar 5 14:35:04 2015 +0200
AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2
Make the build tolerate re-definitions.
Change-Id: Ia7505837c70b1f749262508b26576e95c7865576 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/amd/car/cache_as_ram.inc | 4 ++-- src/include/cpu/amd/mtrr.h | 10 ++-------- src/vendorcode/amd/agesa/f10/AGESA.h | 8 ++------ src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h | 2 +- src/vendorcode/amd/agesa/f12/AGESA.h | 8 ++------ src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h | 2 +- src/vendorcode/amd/agesa/f14/AGESA.h | 8 ++------ src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h | 2 +- src/vendorcode/amd/agesa/f15/AGESA.h | 10 ++-------- src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h | 2 +- src/vendorcode/amd/agesa/f16kb/AGESA.h | 4 ---- 11 files changed, 16 insertions(+), 44 deletions(-)
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index dadf8f7..f7dec30 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -468,8 +468,8 @@ all_mtrr_msrs: .long IORRMask_MSR(1)
/* Top of memory MTRR MSRs */ - .long TOP_MEM_MSR - .long TOP_MEM2_MSR + .long TOP_MEM + .long TOP_MEM2
.long 0x000 /* NULL, end of table */
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index a9e672b..1dc53b0 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -25,14 +25,8 @@ #define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg)) #define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
-#define TOP_MEM_MSR 0xC001001A -#define TOP_MEM2_MSR 0xC001001D -#ifndef TOP_MEM - #define TOP_MEM TOP_MEM_MSR -#endif -#ifndef TOP_MEM2 - #define TOP_MEM2 TOP_MEM2_MSR -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul
#define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h index c38bf40..a128116 100644 --- a/src/vendorcode/amd/agesa/f10/AGESA.h +++ b/src/vendorcode/amd/agesa/f10/AGESA.h @@ -1012,12 +1012,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -#ifndef TOP_MEM - #define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 - #define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h index 34d2568..1777c5d 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h @@ -92,7 +92,7 @@ #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0
diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h index 9660f35..abe72b6 100644 --- a/src/vendorcode/amd/agesa/f12/AGESA.h +++ b/src/vendorcode/amd/agesa/f12/AGESA.h @@ -1279,12 +1279,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -#ifndef TOP_MEM -#define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 -#define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h index 29f4070..b871845 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h @@ -101,7 +101,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0
diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index a8ede95..d997ad1 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -1129,12 +1129,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -#ifndef TOP_MEM -#define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 -#define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h index 6369bfc..a6f6c78 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h @@ -98,7 +98,7 @@ #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0
diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h index 6b0171b..ffa37ae 100644 --- a/src/vendorcode/amd/agesa/f15/AGESA.h +++ b/src/vendorcode/amd/agesa/f15/AGESA.h @@ -1418,14 +1418,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -//#define TOP_MEM 0xC001001A -//#define TOP_MEM2 0xC001001D -#ifndef TOP_MEM - #define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 - #define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h index 050ec53..d010347 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h @@ -116,7 +116,7 @@ CpuLateInitApTask ( #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0
diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index 3e58d23..6c2f19c 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -1590,12 +1590,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010ul -#ifndef TOP_MEM #define TOP_MEM 0xC001001Aul -#endif -#ifndef TOP_MEM2 #define TOP_MEM2 0xC001001Dul -#endif #define HWCR 0xC0010015ul #define NB_CFG 0xC001001Ful
-
Kyösti Mälkki