[S] Change in coreboot[master]: soc/intel/{adl, cmn}: Allow config to select the OCP workaround

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68309 )

(

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/{adl, cmn}: Allow config to select the OCP workaround
......................................................................

soc/intel/{adl, cmn}: Allow config to select the OCP workaround

This patch introduces a config option for SoC code to choose
the applicable SoC workaround.

For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE`
to apply UFS OCP timeout disable workaround.

At present ADL SoC only selects so, and in future MTL and others
should check with Intel prior selecting this kconfig.

It's the placeholder to add more workaround in required going forward.

BUG=none
TEST=Able to build and boot Google/Brya.

Signed-off-by: Subrata Banik 
Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309
Reviewed-by: Reka Norman 
Reviewed-by: Kangheui Won 
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi/ufs.asl
3 files changed, 47 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kangheui Won: Looks good to me, but someone else must approve
  Reka Norman: Looks good to me, approved
  Eric Lai: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 92a8c06..fe7b3a2 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -425,6 +425,13 @@
    help
      Enables ACPI entry to provide silicon type information to IPU kernel driver.

+config ALDERLAKE_ENABLE_SOC_WORKAROUND
+	bool
+	default y
+	select SOC_INTEL_UFS_OCP_TIMER_DISABLE
+	help
+	  Selects the workarounds applicable for Alder Lake SoC.
+
 choice
    prompt "Multiprocessor (MP) Initialization configuration to use"
    default USE_FSP_MP_INIT
diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig
index e21584c..2b102bc 100644
--- a/src/soc/intel/common/block/acpi/Kconfig
+++ b/src/soc/intel/common/block/acpi/Kconfig
@@ -49,4 +49,11 @@
    help
      Defines hybrid CPU specific ACPI helper functions.

+config SOC_INTEL_UFS_OCP_TIMER_DISABLE
+	bool
+	help
+	  OCP Timer need to be disabled in SCS UFS IOSF Bridge to
+	  work around the Silicon Issue due to which LTR mechanism
+	  doesn't work.
+
 endif
diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl
index 41c14d7..f7cb9f3 100644
--- a/src/soc/intel/common/block/acpi/acpi/ufs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl
@@ -67,8 +67,10 @@
    		/* Set BIT[1:0] = 00b - Power State D0 */
    		PSTA &= 0xFFFFFFFC

+#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
    		/* Disable OCP Timer in SCS UFS IOSF Bridge */
    		OCPD ()
+#endif
    	}

Method (_PS3, 0, Serialized)
@@ -79,7 +81,9 @@

Method (_INI)
    	{
+#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
    		OCPD ()
+#endif
    	}
    }
 }