Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59083 )
Change subject: mb/google/guybrush: Add variant_tpm_gpio_table ......................................................................
mb/google/guybrush: Add variant_tpm_gpio_table
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from early_gpio_table. This allows for initializing TPM gpios separately from other gpios.
BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush
Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Signed-off-by: Rob Barnes robbarnes@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083 Reviewed-by: Karthik Ramasubramanian kramasub@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/guybrush/bootblock.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c M src/mainboard/google/guybrush/verstage.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 8 files changed, 92 insertions(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 1154444..2791a8f 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -53,6 +53,9 @@ gpios = variant_espi_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios);
+ gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); + gpios = variant_early_gpio_table(&num_gpios); override_gpios = variant_early_override_gpio_table(&override_num_gpios); gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios); diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 0720bc2..c9b533e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -199,16 +199,6 @@ /* WWAN_RST_L */ PAD_GPO(GPIO_24, LOW),
-/* Enable ESPI, GSC Interrupt & I2C Communication */ - /* Unused */ - PAD_NC(GPIO_3), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Enable UART 0 */ /* UART0_RXD */ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), @@ -237,6 +227,15 @@ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), };
+static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + /* Power-on timing requirements: * Fibocom 350-GL: * FCP0# goes high (GPIO 6) to Reset# high (GPIO 24): 20ms min @@ -353,3 +352,9 @@ *size = ARRAY_SIZE(espi_gpio_table); return espi_gpio_table; } + +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 0dc6c7b..b50a590 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -43,6 +43,9 @@ /* This function provides GPIO settings for eSPI bus. */ const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size);
+/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); + bool variant_has_pcie_wwan(void);
void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index e90f4a3..fe2dcd1 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -44,10 +44,6 @@ static const struct soc_amd_gpio override_early_gpio_table[] = { /* BID == 1: SD_AUX_RESET_L */ PAD_GPO(GPIO_70, LOW), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Unused */ - PAD_NC(GPIO_85), };
/* This table is used by guybrush variant with board version < 2. */ @@ -56,6 +52,15 @@ PAD_GPO(GPIO_70, HIGH), };
+static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -92,3 +97,9 @@
return NULL; } + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index a2a0e93..00fd964 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -39,8 +39,6 @@ };
static const struct soc_amd_gpio override_early_gpio_table[] = { - /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_NC(GPIO_18), };
@@ -48,6 +46,27 @@ PAD_NC(GPIO_18), };
+ +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + +/* This table is used by nipperkin variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -72,3 +91,16 @@ *size = ARRAY_SIZE(override_pcie_gpio_table); return override_pcie_gpio_table; } + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + uint32_t board_version = board_id(); + + if (board_version < 2) { + *size = ARRAY_SIZE(bid1_tpm_gpio_table); + return bid1_tpm_gpio_table; + } + + *size = ARRAY_SIZE(bid2_tpm_gpio_table); + return bid2_tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index 17481d2..35bfa0a 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -46,3 +46,15 @@ dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; pm_io_write32(PM_ACPI_CONF, dword); } + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index dbdf2f2..ef8a9da 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -49,6 +49,7 @@ uint32_t unmap_fch_devices(void); uint32_t verstage_soc_early_init(void); void verstage_mainboard_espi_init(void); +void verstage_mainboard_tpm_init(void); void verstage_soc_aoac_init(void); void verstage_soc_espi_init(void); void verstage_soc_i2c_init(void); diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 8fc2732..71f07c0 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -25,7 +25,9 @@
void __weak verstage_mainboard_early_init(void) {} void __weak verstage_mainboard_espi_init(void) {} +void __weak verstage_mainboard_tpm_init(void) {} void __weak verstage_mainboard_init(void) {} + uint32_t __weak get_max_workbuf_size(uint32_t *size) { /* This svc only exists in picasso and deprecated for later platforms. @@ -238,15 +240,19 @@ printk(BIOS_DEBUG, "calling verstage_mainboard_espi_init\n"); verstage_mainboard_espi_init();
+ printk(BIOS_DEBUG, "calling verstage_soc_espi_init\n"); + verstage_soc_espi_init(); + + printk(BIOS_DEBUG, "calling verstage_mainboard_tpm_init\n"); + /* mainboard_tpm_init may check board_id, so make sure espi is ready first */ + verstage_mainboard_tpm_init(); + printk(BIOS_DEBUG, "calling verstage_mainboard_early_init\n"); verstage_mainboard_early_init();
svc_write_postcode(POSTCODE_LATE_INIT); fch_io_enable_legacy_io();
- printk(BIOS_DEBUG, "calling verstage_soc_espi_init\n"); - verstage_soc_espi_init(); - printk(BIOS_DEBUG, "calling verstage_soc_aoac_init\n"); verstage_soc_aoac_init();
-
Felix Held (Code Review)