Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47047 )
Change subject: [WIP] move broadwell pch as lynxpoint-lp ......................................................................
[WIP] move broadwell pch as lynxpoint-lp
Change-Id: I5b55f90e6366b83c75834d7ef57ff2ebdce972b6 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_bdw/gpio.c M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/ramstage.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c A src/southbridge/intel/lynxpoint_lp/Kconfig R src/southbridge/intel/lynxpoint_lp/Makefile.inc R src/southbridge/intel/lynxpoint_lp/acpi/globalnvs.asl R src/southbridge/intel/lynxpoint_lp/adsp.c R src/southbridge/intel/lynxpoint_lp/adsp.h R src/southbridge/intel/lynxpoint_lp/bootblock.c R src/southbridge/intel/lynxpoint_lp/chip.h R src/southbridge/intel/lynxpoint_lp/early_pch.c R src/southbridge/intel/lynxpoint_lp/ehci.h R src/southbridge/intel/lynxpoint_lp/elog.c R src/southbridge/intel/lynxpoint_lp/fadt.c R src/southbridge/intel/lynxpoint_lp/finalize.c R src/southbridge/intel/lynxpoint_lp/gpio.c R src/southbridge/intel/lynxpoint_lp/gpio.h R src/southbridge/intel/lynxpoint_lp/hda.c R src/southbridge/intel/lynxpoint_lp/iobp.c R src/southbridge/intel/lynxpoint_lp/iobp.h R src/southbridge/intel/lynxpoint_lp/lpc.c R src/southbridge/intel/lynxpoint_lp/lpc.h R src/southbridge/intel/lynxpoint_lp/me.c R src/southbridge/intel/lynxpoint_lp/me.h R src/southbridge/intel/lynxpoint_lp/me_status.c R src/southbridge/intel/lynxpoint_lp/nvs.h R src/southbridge/intel/lynxpoint_lp/pch.c R src/southbridge/intel/lynxpoint_lp/pch.h R src/southbridge/intel/lynxpoint_lp/pcie.c R src/southbridge/intel/lynxpoint_lp/pm.h R src/southbridge/intel/lynxpoint_lp/pmutil.c R src/southbridge/intel/lynxpoint_lp/power_state.c R src/southbridge/intel/lynxpoint_lp/rcba.h R src/southbridge/intel/lynxpoint_lp/sata.c R src/southbridge/intel/lynxpoint_lp/sata.h R src/southbridge/intel/lynxpoint_lp/serialio.c R src/southbridge/intel/lynxpoint_lp/serialio.h R src/southbridge/intel/lynxpoint_lp/smbus.c R src/southbridge/intel/lynxpoint_lp/smbus.h R src/southbridge/intel/lynxpoint_lp/smi.c R src/southbridge/intel/lynxpoint_lp/smihandler.c R src/southbridge/intel/lynxpoint_lp/spi.h R src/southbridge/intel/lynxpoint_lp/uart.c R src/southbridge/intel/lynxpoint_lp/usb_debug.c R src/southbridge/intel/lynxpoint_lp/usb_ehci.c R src/southbridge/intel/lynxpoint_lp/usb_xhci.c R src/southbridge/intel/lynxpoint_lp/xhci.h 59 files changed, 121 insertions(+), 106 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47047/1
diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 19502ed..c3827e5 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -2,7 +2,7 @@
#include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <soc/intel/broadwell/pch/nvs.h> +#include <southbridge/intel/lynxpoint_lp/nvs.h>
void acpi_create_gnvs(struct global_nvs *gnvs) { diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 0575a98..84131b1 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -27,7 +27,7 @@ device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio
- chip soc/intel/broadwell/pch + chip southbridge/intel/lynxpoint_lp # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index f0c67bad..669fec9 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -13,7 +13,7 @@ #include <soc/intel/broadwell/acpi/platform.asl>
/* Global NVS and variables */ - #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint_lp/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/purism/librem_bdw/gpio.c b/src/mainboard/purism/librem_bdw/gpio.c index 4ef248a..d44cc20 100644 --- a/src/mainboard/purism/librem_bdw/gpio.c +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/intel/broadwell/pch/gpio.h> +#include <southbridge/intel/lynxpoint_lp/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 0 */ diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index 256077c..b05bbef 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell
device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/lynxpoint_lp # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index d88c19c..21acfe6 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell
device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/lynxpoint_lp # Port 0 is HDD # Port 1 is M.2 NGFF register "sata_port_map" = "0x3" diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 02cd1c2..c03b034 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -5,55 +5,16 @@
if SOC_INTEL_BROADWELL
-config INTEL_LYNXPOINT_LP - bool - default y if SOC_INTEL_BROADWELL - config SOC_SPECIFIC_OPTIONS def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CPU_INTEL_HASWELL - select HAVE_SMI_HANDLER - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select HAVE_USBDEBUG - select IOAPIC - select REG_SCRIPT - select RTC - select SPI_FLASH - select SOC_INTEL_COMMON - select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT select INTEL_GMA_ACPI - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - -config PCIEXP_ASPM - bool - default y - -config PCIEXP_AER - bool - default y - -config PCIEXP_COMMON_CLOCK - bool - default y - -config PCIEXP_CLK_PM - bool - default y - -config PCIEXP_L1_SUB_STATE - bool - default y + select REG_SCRIPT + select SOC_INTEL_COMMON + select SOUTHBRIDGE_INTEL_LYNXPOINT_LP
config BROADWELL_VBOOT_IN_BOOTBLOCK depends on VBOOT @@ -162,17 +123,6 @@ default 0xd6000000 depends on INTEL_PCH_UART_CONSOLE
-config EHCI_BAR - hex - default 0xd8000000 - -config SERIRQ_CONTINUOUS_MODE - bool - default y - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - config HAVE_REFCODE_BLOB depends on ARCH_X86 bool "An external reference code blob should be put into cbfs." diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 3f06913..b8c52f4 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,7 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
-subdirs-y += pch - bootblock-y += bootblock.c
romstage-y += early_init.c diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 300b7e7..cfaf6a9 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -18,8 +18,8 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pch.h> -#include <soc/intel/broadwell/pch/pm.h> +#include <southbridge/intel/lynxpoint_lp/pch.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include <soc/intel/broadwell/chip.h>
#include "haswell.h" diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 6c6dc20..e2630d1 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h>
#include <soc/intel/broadwell/haswell.h> -#include "pch/pch.h" +#include <southbridge/intel/lynxpoint_lp/pch.h>
/* * 16.6 System Agent Configuration Locking diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 0c881c2..51e1ad2 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -16,7 +16,7 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> -#include <soc/intel/broadwell/pch/pm.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include <soc/intel/broadwell/chip.h> #include <security/vboot/vbnv.h> #include <types.h> diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 670b0f5..28c8d60 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -5,10 +5,10 @@ #include <console/console.h> #include <device/device.h> #include <string.h> -#include <soc/intel/broadwell/pch/pm.h>
#include <soc/intel/broadwell/chip.h> -#include <soc/intel/broadwell/pch/nvs.h> +#include <southbridge/intel/lynxpoint_lp/nvs.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include "ramstage.h"
/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 4ec1fc2..d066893 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -8,7 +8,7 @@ #include <program_loading.h> #include <rmodule.h> #include <stage_cache.h> -#include <soc/intel/broadwell/pch/pm.h> +#include <southbridge/intel/lynxpoint_lp/pm.h>
#include "ramstage.h" #include "pei_data.h" diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index b02b234..e336e76 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -11,7 +11,7 @@ #include <soc/intel/broadwell/romstage.h>
#include <soc/intel/broadwell/haswell.h> -#include "pch/pch.h" +#include <southbridge/intel/lynxpoint_lp/pch.h>
/* FIXME: Needs an update */ static struct { diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index c47d60f..cfae2c2 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -8,7 +8,6 @@ #include <cpu/intel/haswell/haswell.h> #include <elog.h> #include <romstage_handoff.h> -#include <soc/intel/broadwell/pch/pm.h> #include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> #include <stdint.h> @@ -16,9 +15,10 @@
#include "haswell.h" #include "pei_data.h" -#include "pch/gpio.h" -#include "pch/me.h" -#include "pch/pch.h" +#include <southbridge/intel/lynxpoint_lp/gpio.h> +#include <southbridge/intel/lynxpoint_lp/me.h> +#include <southbridge/intel/lynxpoint_lp/pch.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include "raminit.h"
/* Entry from cpu/intel/car/romstage.c. */ diff --git a/src/southbridge/intel/lynxpoint_lp/Kconfig b/src/southbridge/intel/lynxpoint_lp/Kconfig new file mode 100644 index 0000000..fb869961 --- /dev/null +++ b/src/southbridge/intel/lynxpoint_lp/Kconfig @@ -0,0 +1,62 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOUTHBRIDGE_INTEL_LYNXPOINT_LP + bool + +if SOUTHBRIDGE_INTEL_LYNXPOINT_LP + +config INTEL_LYNXPOINT_LP + bool + default y if SOUTHBRIDGE_INTEL_LYNXPOINT_LP + +config SOUTH_BRIDGE_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select HAVE_SMI_HANDLER + select HAVE_USBDEBUG + select IOAPIC + select INTEL_DESCRIPTOR_MODE_CAPABLE + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select RTC + select SPI_FLASH + +config EHCI_BAR + hex + default 0xd8000000 + +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +config PCIEXP_ASPM + bool + default y + +config PCIEXP_AER + bool + default y + +config PCIEXP_COMMON_CLOCK + bool + default y + +config PCIEXP_CLK_PM + bool + default y + +config PCIEXP_L1_SUB_STATE + bool + default y + +endif diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/southbridge/intel/lynxpoint_lp/Makefile.inc similarity index 93% rename from src/soc/intel/broadwell/pch/Makefile.inc rename to src/southbridge/intel/lynxpoint_lp/Makefile.inc index 1ebe324f..6d18c9f 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/southbridge/intel/lynxpoint_lp/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT_LP),y) + bootblock-y += bootblock.c
ramstage-y += adsp.c @@ -37,3 +39,5 @@ smm-y += usb_xhci.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c + +endif diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint_lp/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/globalnvs.asl rename to src/southbridge/intel/lynxpoint_lp/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/southbridge/intel/lynxpoint_lp/adsp.c similarity index 96% rename from src/soc/intel/broadwell/pch/adsp.c rename to src/southbridge/intel/lynxpoint_lp/adsp.c index 03da7d2..fa7e2d9 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/southbridge/intel/lynxpoint_lp/adsp.c @@ -7,9 +7,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <soc/intel/broadwell/pch/chip.h>
#include "adsp.h" +#include "chip.h" #include "iobp.h" #include "nvs.h" #include "pch.h" @@ -17,7 +17,7 @@
static void adsp_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32;
diff --git a/src/soc/intel/broadwell/pch/adsp.h b/src/southbridge/intel/lynxpoint_lp/adsp.h similarity index 100% rename from src/soc/intel/broadwell/pch/adsp.h rename to src/southbridge/intel/lynxpoint_lp/adsp.h diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/southbridge/intel/lynxpoint_lp/bootblock.c similarity index 98% rename from src/soc/intel/broadwell/pch/bootblock.c rename to src/southbridge/intel/lynxpoint_lp/bootblock.c index 3fe2568..dc7df72 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/southbridge/intel/lynxpoint_lp/bootblock.c @@ -3,12 +3,12 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> #include <soc/intel/broadwell/romstage.h> #include <southbridge/intel/common/early_spi.h>
#include "lpc.h" #include "pch.h" +#include "pm.h" #include "rcba.h" #include "spi.h"
diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/southbridge/intel/lynxpoint_lp/chip.h similarity index 96% rename from src/soc/intel/broadwell/pch/chip.h rename to src/southbridge/intel/lynxpoint_lp/chip.h index 2164a31..470ef23 100644 --- a/src/soc/intel/broadwell/pch/chip.h +++ b/src/southbridge/intel/lynxpoint_lp/chip.h @@ -5,7 +5,7 @@
#include <stdint.h>
-struct soc_intel_broadwell_pch_config { +struct southbridge_intel_lynxpoint_lp_config { /* GPE configuration */ uint32_t gpe0_en_1; uint32_t gpe0_en_2; diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/southbridge/intel/lynxpoint_lp/early_pch.c similarity index 93% rename from src/soc/intel/broadwell/pch/early_pch.c rename to src/southbridge/intel/lynxpoint_lp/early_pch.c index 4f59397..d9c927a 100644 --- a/src/soc/intel/broadwell/pch/early_pch.c +++ b/src/southbridge/intel/lynxpoint_lp/early_pch.c @@ -5,11 +5,11 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> -#include <soc/intel/broadwell/pch/chip.h>
+#include "chip.h" #include "lpc.h" #include "pch.h" +#include "pm.h" #include "rcba.h" #include "smbus.h"
@@ -56,7 +56,7 @@ if (!dev || !dev->chip_info) return;
- const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_lynxpoint_lp_config *config = dev->chip_info;
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/pch/ehci.h b/src/southbridge/intel/lynxpoint_lp/ehci.h similarity index 100% rename from src/soc/intel/broadwell/pch/ehci.h rename to src/southbridge/intel/lynxpoint_lp/ehci.h diff --git a/src/soc/intel/broadwell/pch/elog.c b/src/southbridge/intel/lynxpoint_lp/elog.c similarity index 100% rename from src/soc/intel/broadwell/pch/elog.c rename to src/southbridge/intel/lynxpoint_lp/elog.c diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/southbridge/intel/lynxpoint_lp/fadt.c similarity index 98% rename from src/soc/intel/broadwell/pch/fadt.c rename to src/southbridge/intel/lynxpoint_lp/fadt.c index 39e3508..83242d3 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/southbridge/intel/lynxpoint_lp/fadt.c @@ -3,8 +3,9 @@ #include <acpi/acpi.h> #include <cpu/x86/smm.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> + #include "chip.h" +#include "pm.h"
void acpi_fill_fadt(acpi_fadt_t *fadt) { diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/southbridge/intel/lynxpoint_lp/finalize.c similarity index 100% rename from src/soc/intel/broadwell/pch/finalize.c rename to src/southbridge/intel/lynxpoint_lp/finalize.c diff --git a/src/soc/intel/broadwell/pch/gpio.c b/src/southbridge/intel/lynxpoint_lp/gpio.c similarity index 98% rename from src/soc/intel/broadwell/pch/gpio.c rename to src/southbridge/intel/lynxpoint_lp/gpio.c index d61670d..dd480c3 100644 --- a/src/soc/intel/broadwell/pch/gpio.c +++ b/src/southbridge/intel/lynxpoint_lp/gpio.c @@ -5,9 +5,9 @@ #include <device/device.h> #include <device/pci.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h>
#include "gpio.h" +#include "pm.h"
/* * This function will return a number that indicates which PIRQ diff --git a/src/soc/intel/broadwell/pch/gpio.h b/src/southbridge/intel/lynxpoint_lp/gpio.h similarity index 100% rename from src/soc/intel/broadwell/pch/gpio.h rename to src/southbridge/intel/lynxpoint_lp/gpio.h diff --git a/src/soc/intel/broadwell/pch/hda.c b/src/southbridge/intel/lynxpoint_lp/hda.c similarity index 100% rename from src/soc/intel/broadwell/pch/hda.c rename to src/southbridge/intel/lynxpoint_lp/hda.c diff --git a/src/soc/intel/broadwell/pch/iobp.c b/src/southbridge/intel/lynxpoint_lp/iobp.c similarity index 100% rename from src/soc/intel/broadwell/pch/iobp.c rename to src/southbridge/intel/lynxpoint_lp/iobp.c diff --git a/src/soc/intel/broadwell/pch/iobp.h b/src/southbridge/intel/lynxpoint_lp/iobp.h similarity index 100% rename from src/soc/intel/broadwell/pch/iobp.h rename to src/southbridge/intel/lynxpoint_lp/iobp.h diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/southbridge/intel/lynxpoint_lp/lpc.c similarity index 97% rename from src/soc/intel/broadwell/pch/lpc.c rename to src/southbridge/intel/lynxpoint_lp/lpc.c index d62a94c..4824e4c 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/southbridge/intel/lynxpoint_lp/lpc.c @@ -21,13 +21,13 @@
#include <soc/intel/broadwell/memmap.h> #include <soc/intel/broadwell/haswell.h> -#include <soc/intel/broadwell/pch/pm.h> -#include <soc/intel/broadwell/pch/chip.h>
+#include "chip.h" #include "lpc.h" #include "iobp.h" #include "nvs.h" #include "pch.h" +#include "pm.h" #include "rcba.h" #include "gpio.h"
@@ -173,7 +173,7 @@ printk(BIOS_INFO, "Set power %s after power failure.\n", state);
if (dev->chip_info) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_lynxpoint_lp_config *config = dev->chip_info;
/* GPE setup based on device tree configuration */ enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, @@ -337,7 +337,7 @@
static void pch_init_deep_sx(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_lynxpoint_lp_config *config = dev->chip_info;
if (!config) return; @@ -587,7 +587,7 @@
/* LPC Generic IO Decode range. */ if (dev->chip_info) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_lynxpoint_lp_config *config = dev->chip_info; pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); diff --git a/src/soc/intel/broadwell/pch/lpc.h b/src/southbridge/intel/lynxpoint_lp/lpc.h similarity index 100% rename from src/soc/intel/broadwell/pch/lpc.h rename to src/southbridge/intel/lynxpoint_lp/lpc.h diff --git a/src/soc/intel/broadwell/pch/me.c b/src/southbridge/intel/lynxpoint_lp/me.c similarity index 99% rename from src/soc/intel/broadwell/pch/me.c rename to src/southbridge/intel/lynxpoint_lp/me.c index 3b27b91..89ecca6 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/southbridge/intel/lynxpoint_lp/me.c @@ -20,13 +20,13 @@ #include <string.h> #include <delay.h> #include <elog.h> -#include <soc/intel/broadwell/pch/chip.h>
#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif
+#include "chip.h" #include "me.h" #include "pch.h" #include "rcba.h" @@ -948,7 +948,7 @@ /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; diff --git a/src/soc/intel/broadwell/pch/me.h b/src/southbridge/intel/lynxpoint_lp/me.h similarity index 100% rename from src/soc/intel/broadwell/pch/me.h rename to src/southbridge/intel/lynxpoint_lp/me.h diff --git a/src/soc/intel/broadwell/pch/me_status.c b/src/southbridge/intel/lynxpoint_lp/me_status.c similarity index 100% rename from src/soc/intel/broadwell/pch/me_status.c rename to src/southbridge/intel/lynxpoint_lp/me_status.c diff --git a/src/soc/intel/broadwell/pch/nvs.h b/src/southbridge/intel/lynxpoint_lp/nvs.h similarity index 100% rename from src/soc/intel/broadwell/pch/nvs.h rename to src/southbridge/intel/lynxpoint_lp/nvs.h diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/southbridge/intel/lynxpoint_lp/pch.c similarity index 96% rename from src/soc/intel/broadwell/pch/pch.c rename to src/southbridge/intel/lynxpoint_lp/pch.c index b4315b6..882dabe 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/southbridge/intel/lynxpoint_lp/pch.c @@ -165,7 +165,7 @@ } }
-static void broadwell_pch_enable_dev(struct device *dev) +static void pch_enable(struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) return; @@ -196,9 +196,9 @@ } }
-struct chip_operations soc_intel_broadwell_pch_ops = { - CHIP_NAME("Intel Broadwell PCH") - .enable_dev = &broadwell_pch_enable_dev, +struct chip_operations southbridge_intel_lynxpoint_lp_ops = { + CHIP_NAME("Intel Lynx Point LP PCH") + .enable_dev = pch_enable, };
#endif diff --git a/src/soc/intel/broadwell/pch/pch.h b/src/southbridge/intel/lynxpoint_lp/pch.h similarity index 100% rename from src/soc/intel/broadwell/pch/pch.h rename to src/southbridge/intel/lynxpoint_lp/pch.h diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/southbridge/intel/lynxpoint_lp/pcie.c similarity index 98% rename from src/soc/intel/broadwell/pch/pcie.c rename to src/southbridge/intel/lynxpoint_lp/pcie.c index 8bf7d3d..1a78bab 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/southbridge/intel/lynxpoint_lp/pcie.c @@ -7,11 +7,11 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "rcba.h" -#include <soc/intel/broadwell/pch/chip.h> #include <delay.h>
#include <cpu/intel/haswell/haswell.h> + +#include "chip.h" #include "gpio.h" #include "iobp.h" #include "pch.h" @@ -121,7 +121,7 @@ root_port_config_update_gbe_port();
pci_or_config8(dev, 0xe2, 3 << 4); - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; }
@@ -435,7 +435,7 @@
static void pch_pcie_early(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev);
diff --git a/src/soc/intel/broadwell/pch/pm.h b/src/southbridge/intel/lynxpoint_lp/pm.h similarity index 100% rename from src/soc/intel/broadwell/pch/pm.h rename to src/southbridge/intel/lynxpoint_lp/pm.h diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/southbridge/intel/lynxpoint_lp/pmutil.c similarity index 99% rename from src/soc/intel/broadwell/pch/pmutil.c rename to src/southbridge/intel/lynxpoint_lp/pmutil.c index e8af6cc..8ba8739 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/southbridge/intel/lynxpoint_lp/pmutil.c @@ -14,13 +14,13 @@ #include <device/pci_def.h> #include <console/console.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> #include <security/vboot/vbnv.h> #include <stdint.h>
#include "gpio.h" #include "lpc.h" #include "pch.h" +#include "pm.h"
static inline uint16_t get_gpiobase(void) { diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/southbridge/intel/lynxpoint_lp/power_state.c similarity index 98% rename from src/soc/intel/broadwell/pch/power_state.c rename to src/southbridge/intel/lynxpoint_lp/power_state.c index a39822a..0078b04 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/southbridge/intel/lynxpoint_lp/power_state.c @@ -9,7 +9,6 @@ #include <device/pci_def.h> #include <string.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> #include <soc/intel/broadwell/romstage.h>
#include "lpc.h" diff --git a/src/soc/intel/broadwell/pch/rcba.h b/src/southbridge/intel/lynxpoint_lp/rcba.h similarity index 100% rename from src/soc/intel/broadwell/pch/rcba.h rename to src/southbridge/intel/lynxpoint_lp/rcba.h diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/southbridge/intel/lynxpoint_lp/sata.c similarity index 96% rename from src/soc/intel/broadwell/pch/sata.c rename to src/southbridge/intel/lynxpoint_lp/sata.c index e9d70f1..c33088b 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/southbridge/intel/lynxpoint_lp/sata.c @@ -8,8 +8,8 @@ #include <device/pci_ids.h> #include <delay.h> #include <southbridge/intel/common/abar.h> -#include <soc/intel/broadwell/pch/chip.h>
+#include "chip.h" #include "iobp.h" #include "rcba.h" #include "sata.h" @@ -37,7 +37,7 @@ }
static void sata_configure_devslp( - const struct soc_intel_broadwell_pch_config *config, + const struct southbridge_intel_lynxpoint_lp_config *config, const uintptr_t abar) { union abar_reg_cap_2 abar_cap_2 = { @@ -71,7 +71,7 @@
static void sata_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); u32 reg32;
printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); @@ -272,7 +272,7 @@ static void sata_enable(struct device *dev) { /* Get the chip configuration */ - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev);
/* * Set SATA controller mode early so the resource allocator can diff --git a/src/soc/intel/broadwell/pch/sata.h b/src/southbridge/intel/lynxpoint_lp/sata.h similarity index 100% rename from src/soc/intel/broadwell/pch/sata.h rename to src/southbridge/intel/lynxpoint_lp/sata.h diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/southbridge/intel/lynxpoint_lp/serialio.c similarity index 98% rename from src/soc/intel/broadwell/pch/serialio.c rename to src/southbridge/intel/lynxpoint_lp/serialio.c index 0c079be..ce95237 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/southbridge/intel/lynxpoint_lp/serialio.c @@ -7,8 +7,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/intel/broadwell/pch/chip.h>
+#include "chip.h" #include "iobp.h" #include "nvs.h" #include "pch.h" @@ -155,7 +155,7 @@
static void serialio_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1;
diff --git a/src/soc/intel/broadwell/pch/serialio.h b/src/southbridge/intel/lynxpoint_lp/serialio.h similarity index 100% rename from src/soc/intel/broadwell/pch/serialio.h rename to src/southbridge/intel/lynxpoint_lp/serialio.h diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/southbridge/intel/lynxpoint_lp/smbus.c similarity index 100% rename from src/soc/intel/broadwell/pch/smbus.c rename to src/southbridge/intel/lynxpoint_lp/smbus.c diff --git a/src/soc/intel/broadwell/pch/smbus.h b/src/southbridge/intel/lynxpoint_lp/smbus.h similarity index 100% rename from src/soc/intel/broadwell/pch/smbus.h rename to src/southbridge/intel/lynxpoint_lp/smbus.h diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/southbridge/intel/lynxpoint_lp/smi.c similarity index 96% rename from src/soc/intel/broadwell/pch/smi.c rename to src/southbridge/intel/lynxpoint_lp/smi.c index a1cdfda..a157265 100644 --- a/src/soc/intel/broadwell/pch/smi.c +++ b/src/southbridge/intel/lynxpoint_lp/smi.c @@ -6,7 +6,8 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> -#include <soc/intel/broadwell/pch/pm.h> + +#include "pm.h"
void smm_southbridge_clear_state(void) { diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/southbridge/intel/lynxpoint_lp/smihandler.c similarity index 100% rename from src/soc/intel/broadwell/pch/smihandler.c rename to src/southbridge/intel/lynxpoint_lp/smihandler.c diff --git a/src/soc/intel/broadwell/pch/spi.h b/src/southbridge/intel/lynxpoint_lp/spi.h similarity index 100% rename from src/soc/intel/broadwell/pch/spi.h rename to src/southbridge/intel/lynxpoint_lp/spi.h diff --git a/src/soc/intel/broadwell/pch/uart.c b/src/southbridge/intel/lynxpoint_lp/uart.c similarity index 100% rename from src/soc/intel/broadwell/pch/uart.c rename to src/southbridge/intel/lynxpoint_lp/uart.c diff --git a/src/soc/intel/broadwell/pch/usb_debug.c b/src/southbridge/intel/lynxpoint_lp/usb_debug.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_debug.c rename to src/southbridge/intel/lynxpoint_lp/usb_debug.c diff --git a/src/soc/intel/broadwell/pch/usb_ehci.c b/src/southbridge/intel/lynxpoint_lp/usb_ehci.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_ehci.c rename to src/southbridge/intel/lynxpoint_lp/usb_ehci.c diff --git a/src/soc/intel/broadwell/pch/usb_xhci.c b/src/southbridge/intel/lynxpoint_lp/usb_xhci.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_xhci.c rename to src/southbridge/intel/lynxpoint_lp/usb_xhci.c diff --git a/src/soc/intel/broadwell/pch/xhci.h b/src/southbridge/intel/lynxpoint_lp/xhci.h similarity index 100% rename from src/soc/intel/broadwell/pch/xhci.h rename to src/southbridge/intel/lynxpoint_lp/xhci.h
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47047 )
Change subject: [WIP] move broadwell pch as lynxpoint-lp ......................................................................
Abandoned
-
Angel Pons (Code Review)