[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74378 )

Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
......................................................................

vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed

Phoenix supports up to PCIe gen 4 link speeds, so add the missing GEN4
element to the dxio_link_speed_cap enum. The enum value for the PCIe gen
4 link speed was checked against the AGESA reference code.

Bug=b:277815815
TEST=None

Signed-off-by: Felix Held 
Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56
---
M src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/74378/1

diff --git a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
index a260138..368794a 100644
--- a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
@@ -32,6 +32,7 @@
    GEN1,
    GEN2,
    GEN3,
+	GEN4,
    GEN_INVALID		// Max Gen for boundary check
 };