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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61215
to look at the new patch set (#3).
Change subject: device: Add support for PCIe Resizable BARs ......................................................................
device: Add support for PCIe Resizable BARs
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can indicates support for "Resizable BARs" via a PCIe extended capability.
When support this capability is indicated by the device, the size of each BAR is determined in a different way than the normal "moving bits" method. Instead, a pair of capability and control registers is allocated in config space for each BAR, which can be used to both indicate the different sizes the device is capable of supporting for the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and to also inform the device of the size that the allocator actually reserved for the MMIO range.
This patch adds a Kconfig for a mainboard to select if it knows that it will have a device that requires this support during PCI enumeration. If so, there is a corresponding Kconfig to indicate the maximum number of bits of address space to hand out to devices this way (again, limited by what devices can support and each individual system may want to support, but just like above, this number can range from 20 to 63) If the device can support more bits than this Kconfig, the resource request is truncated to the number indicated by this Kconfig.
BUG=b:214443809 TEST=compile (device with this capability not available yet), also verify that no changes are seen in resource allocation for google/brya0 before and after this change.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf --- M src/device/Kconfig M src/device/pci_device.c M src/include/device/pci_def.h M src/include/device/resource.h 4 files changed, 180 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/61215/3