Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57035 )
Change subject: soc/intel/alderlake: set power limits dynamically for thermal ......................................................................
soc/intel/alderlake: set power limits dynamically for thermal
Set power limit values dynamically based on TDP of SKU.
BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board,
Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/systemagent.c 3 files changed, 38 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/57035/1
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 248eedf..79a6c76 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -18,11 +18,15 @@ #include <soc/vr_config.h> #include <stdint.h>
+#define ADL_P_682_28W 28 +#define ADL_P_682_45W 45 + /* Types of different SKUs */ enum soc_intel_alderlake_power_limits { ADL_P_POWER_LIMITS_282_CORE, ADL_P_POWER_LIMITS_482_CORE, - ADL_P_POWER_LIMITS_682_CORE, + ADL_P_POWER_LIMITS_682_28W_CORE, + ADL_P_POWER_LIMITS_682_45W_CORE, ADL_M_POWER_LIMITS_282_CORE, ADL_POWER_LIMITS_COUNT }; @@ -401,4 +405,6 @@
typedef struct soc_intel_alderlake_config config_t;
+u8 get_cpu_tdp(void); + #endif diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 2d5c54e..ee1e7b4 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -12,7 +12,12 @@ .tdp_pl2_override = 64, }"
- register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{ + register "power_limits_config[ADL_P_POWER_LIMITS_682_28W_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 64, + }" + + register "power_limits_config[ADL_P_POWER_LIMITS_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, }" diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index acdaded..e001f92 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -7,6 +7,7 @@ */
#include <console/console.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -14,6 +15,7 @@ #include <intelblocks/power_limit.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> +#include <soc/msr.h> #include <soc/soc_chip.h> #include <soc/systemagent.h>
@@ -46,6 +48,22 @@ ARRAY_SIZE(soc_vtd_resources)); }
+u8 get_cpu_tdp(void) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + unsigned int power_unit, cpu_tdp; + + /* Get units */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (msr.lo & 0xf); + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + cpu_tdp = msr.lo & 0x7fff; + + return (cpu_tdp / power_unit); +} + /* * SoC implementation * @@ -56,6 +74,7 @@ struct soc_power_limits_config *soc_config; struct device *sa; uint16_t sa_pci_id; + u8 tdp; config_t *config;
/* Enable Power Aware Interrupt Routing */ @@ -72,6 +91,8 @@ sa = pcidev_path_on_root(SA_DEVFN_ROOT); sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
+ tdp = get_cpu_tdp(); + /* Choose a power limits configuration based on the SoC SKU type, * differentiated here based on SA PCI ID. */ switch (sa_pci_id) { @@ -82,7 +103,10 @@ soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_482_CORE]; break; case PCI_DEVICE_ID_INTEL_ADL_P_ID_3: - soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_CORE]; + if (tdp == ADL_P_682_28W) + soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_28W_CORE]; + else + soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_45W_CORE]; break; case PCI_DEVICE_ID_INTEL_ADL_M_ID_1: soc_config = &config->power_limits_config[ADL_M_POWER_LIMITS_282_CORE];