[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )

Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
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Patch Set 28:

(1 comment)

File src/soc/intel/pantherlake/gpio.c:

https://review.coreboot.org/c/coreboot/+/83789/comment/e6a38279_cbcbd062?usp... :
PS17, Line 54: 		.port = PID_GPIOCOM0,
> in progress. some further checking needed as it might be different than .port (i.e. […]

Hi Bubrata, It turns out that the port id is 16-bit in PTL. Therefore, cpu_port needs to 16bit in common GPIO header and port_id related defines in common TCSS header for the register field needs to be moved to SOC, including changes in TGL, ADL, MTL. This is out of this PTL SOC scope. Do you want cpu_port and virtual wire parts to be added later or have add two CLs as part of this upstream CL, one for cpu_port width; one for TCSS code change for 16-bit port id? Please let us know.