Change in coreboot[master]: mb/google/zork/: adjust the edp panel power sequence

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chris wang (Code Review)

22 Dec 2020 22 Dec '20

12:47 p.m.

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48865

to review the following change.

Change subject: mb/google/zork/: adjust the edp panel power sequence ......................................................................

mb/google/zork/: adjust the edp panel power sequence

set pwron_varybl_to_blon to 0x5, which mean fw will delay 20ms between backlight on and vary backlight.

BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was pass to system integrated table; measure the power on sequence on dalboz

Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48865/1

diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index b6a886c..11a4ef9 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -29,6 +29,18 @@ register "edp_version" = "0x0" register "edp_table_size" = "0x05"

+ # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, + # and "0" as default vaule + register "edp_pwr_adjust_enable" = "1" + register "pwron_digon_to_De" = "0" + register "pwron_de_to_varybl" = "0" + register "pwrdown_varybloff_to_de" = "0" + register "pwrdown_de_to_digoff" = "0" + register "pwroff_delay" = "0" + register "pwron_varybl_to_blon" = "5" + register "pwrdown_bloff_to_varybloff" = "5" + register "min_allowed_bl_level" = "0" + register "edp_tuningset" = "{ .dp_vs_pemph_level = 0x0, .deemph_6db4 = 0x004b,

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build bot (Jenkins) (Code Review)

22 Dec 22 Dec

12:48 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork/: adjust the edp panel power sequence ......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48865/1/src/mainboard/google/zork/v... File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/1/src/mainboard/google/zork/v... PS1, Line 33: # and "0" as default vaule 'vaule' may be misspelled - perhaps 'value'?

Paul Menzel (Code Review)

28 Dec 28 Dec

2:22 a.m.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork/: adjust the edp panel power sequence ......................................................................

Patch Set 1:

(3 comments)

https://review.coreboot.org/c/coreboot/+/48865/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/48865/1//COMMIT_MSG@7 PS1, Line 7: mb/google/zork/ Please remove the trailing /.

https://review.coreboot.org/c/coreboot/+/48865/1//COMMIT_MSG@9 PS1, Line 9: mean means

https://review.coreboot.org/c/coreboot/+/48865/1//COMMIT_MSG@14 PS1, Line 14: pass passed

build bot (Jenkins) (Code Review)

11 Jan 11 Jan

11:47 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork/: adjust the edp panel power sequence ......................................................................

Patch Set 2:

(1 comment)

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/a3ac6adf_d3fbe96b PS2, Line 33: # and "0" as default vaule 'vaule' may be misspelled - perhaps 'value'?

build bot (Jenkins) (Code Review)

12 Jan 12 Jan

2:06 a.m.

Attention is currently required from: chris wang. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork/: adjust the edp panel power sequence ......................................................................

Patch Set 3:

(1 comment)

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/76e430fd_a86a968c PS3, Line 33: # and "0" as default vaule 'vaule' may be misspelled - perhaps 'value'?

Paul Menzel (Code Review)

2:49 a.m.

Attention is currently required from: chris wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork/: adjust the edp panel power sequence ......................................................................

Patch Set 3:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/48865/comment/07857cf7_9ebc4903 PS3, Line 7: mb/google/zork/ Please remove the trailing slash.

https://review.coreboot.org/c/coreboot/+/48865/comment/74391be9_b02bea52 PS3, Line 14: pass passed

chris wang (Code Review)

5:25 a.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the edp panel power sequence

Attention is currently required from: chris wang. Hello build bot (Jenkins), Chris Wang,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48865

to look at the new patch set (#4).

Change subject: mb/google/zork: adjust the edp panel power sequence ......................................................................

mb/google/zork: adjust the edp panel power sequence

set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight on and vary backlight.

BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on dalboz

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48865/4

chris wang (Code Review)

5:33 a.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the edp panel power sequence

Attention is currently required from: chris wang. Hello build bot (Jenkins), Chris Wang,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48865

to look at the new patch set (#5).

Change subject: mb/google/zork: adjust the edp panel power sequence ......................................................................

mb/google/zork: adjust the edp panel power sequence

set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight on and vary backlight.

BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on dalboz

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48865/5

chris wang (Code Review)

5:35 a.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the edp panel power sequence

Attention is currently required from: Paul Menzel. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork: adjust the edp panel power sequence ......................................................................

Patch Set 5:

(8 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/48865/comment/07f9a9da_1cb58288 PS1, Line 7: mb/google/zork/

...

Please remove the trailing /.

Done

https://review.coreboot.org/c/coreboot/+/48865/comment/85e30f6a_726f21d1 PS1, Line 9: mean

...

means

Done

https://review.coreboot.org/c/coreboot/+/48865/comment/4200c644_61e317a5 PS1, Line 14: pass

...

passed

Done

Commit Message:

https://review.coreboot.org/c/coreboot/+/48865/comment/8f00d2f5_7cd68685 PS3, Line 7: mb/google/zork/

...

Please remove the trailing slash.

Done

https://review.coreboot.org/c/coreboot/+/48865/comment/d8dc3d61_df4eec66 PS3, Line 14: pass

...

passed

Done

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/1ce84dfc_90ccc10d PS1, Line 33: # and "0" as default vaule

...

'vaule' may be misspelled - perhaps 'value'?

done

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/561cf3da_f689423c PS2, Line 33: # and "0" as default vaule

...

'vaule' may be misspelled - perhaps 'value'?

done

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/31727c13_a172b83b PS3, Line 33: # and "0" as default vaule

...

'vaule' may be misspelled - perhaps 'value'?

done

Nikolai Vyssotski (Code Review)

14 Jan 14 Jan

10:52 a.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the edp panel power sequence

Attention is currently required from: Paul Menzel, chris wang. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork: adjust the edp panel power sequence ......................................................................

Patch Set 5:

(1 comment)

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/0333a33b_fa9c2d97 PS5, Line 35: pwron_digon_to_De Perhaps pwron_digon_to_de?

chris wang (Code Review)

21 Jan 21 Jan

5:11 a.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the eDP panel power sequence

Attention is currently required from: Paul Menzel, chris wang. Hello build bot (Jenkins), Chris Wang,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48865

to look at the new patch set (#11).

Change subject: mb/google/zork: adjust the eDP panel power sequence ......................................................................

mb/google/zork: adjust the eDP panel power sequence

set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight on and vary backlight.

BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on dalboz

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48865/11

chris wang (Code Review)

5:12 a.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the eDP panel power sequence

Attention is currently required from: Paul Menzel, Nikolai Vyssotski. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork: adjust the eDP panel power sequence ......................................................................

Patch Set 11:

(1 comment)

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/88df7728_d7aaf784 PS5, Line 35: pwron_digon_to_De

...

Perhaps pwron_digon_to_de?

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/48865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Gerrit-Change-Number: 48865 Gerrit-PatchSet: 11 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Comment-Date: Thu, 21 Jan 2021 13:12:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-MessageType: comment

EricR Lai (Code Review)

24 Jan 24 Jan

8:17 p.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the eDP panel power sequence

Attention is currently required from: Furquan Shaikh, Kangheui Won, Paul Menzel, Nikolai Vyssotski, chris wang. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork: adjust the eDP panel power sequence ......................................................................

Patch Set 13:

(1 comment)

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/5d1cf0d6_210a3987 PS13, Line 32: register "pwron_digon_to_de" = "0" 0 may not needed. due to soc register initial is 0. But up to you.

-- To view, visit https://review.coreboot.org/c/coreboot/+/48865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Gerrit-Change-Number: 48865 Gerrit-PatchSet: 13 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Kangheui Won khwon@chromium.org Gerrit-Reviewer: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: EricR Lai ericr_lai@compal.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Furquan Shaikh furquan@google.com Gerrit-Attention: Kangheui Won khwon@chromium.org Gerrit-Attention: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Attention: chris wang Chris.Wang@amd.com Gerrit-Comment-Date: Mon, 25 Jan 2021 04:17:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

chris wang (Code Review)

9:16 p.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the eDP panel power sequence

Attention is currently required from: Furquan Shaikh, Kangheui Won, Paul Menzel, Nikolai Vyssotski, EricR Lai. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork: adjust the eDP panel power sequence ......................................................................

Patch Set 14:

(1 comment)

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/4747fcaa_7cda3714 PS13, Line 32: register "pwron_digon_to_de" = "0"

...

0 may not needed. due to soc register initial is 0. But up to you.

I would keep the value here, so when people check the panel sequence, they will know hows other sequence is.

-- To view, visit https://review.coreboot.org/c/coreboot/+/48865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Gerrit-Change-Number: 48865 Gerrit-PatchSet: 14 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Kangheui Won khwon@chromium.org Gerrit-Reviewer: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: EricR Lai ericr_lai@compal.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Furquan Shaikh furquan@google.com Gerrit-Attention: Kangheui Won khwon@chromium.org Gerrit-Attention: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Attention: EricR Lai ericr_lai@compal.corp-partner.google.com Gerrit-Comment-Date: Mon, 25 Jan 2021 05:16:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai ericr_lai@compal.corp-partner.google.com Gerrit-MessageType: comment

chris wang (Code Review)

9:17 p.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the eDP panel power sequence

Change subject: mb/google/zork: adjust the eDP panel power sequence ......................................................................

Patch Set 14:

(1 comment)

File src/mainboard/google/zork/variants/vilboz/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/48865/comment/96b6b650_8f7dd0aa PS13, Line 32: register "pwron_digon_to_de" = "0"

...

I would keep the value here, so when people check the panel sequence, they will know hows other sequ […]

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/48865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Gerrit-Change-Number: 48865 Gerrit-PatchSet: 14 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Kangheui Won khwon@chromium.org Gerrit-Reviewer: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: EricR Lai ericr_lai@compal.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Furquan Shaikh furquan@google.com Gerrit-Attention: Kangheui Won khwon@chromium.org Gerrit-Attention: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Attention: EricR Lai ericr_lai@compal.corp-partner.google.com Gerrit-Comment-Date: Mon, 25 Jan 2021 05:17:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: chris wang Chris.Wang@amd.com Comment-In-Reply-To: EricR Lai ericr_lai@compal.corp-partner.google.com Gerrit-MessageType: comment

EricR Lai (Code Review)

9:21 p.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the eDP panel power sequence

Change subject: mb/google/zork: adjust the eDP panel power sequence ......................................................................

Patch Set 14: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/48865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Gerrit-Change-Number: 48865 Gerrit-PatchSet: 14 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: EricR Lai ericr_lai@compal.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Kangheui Won khwon@chromium.org Gerrit-Reviewer: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Furquan Shaikh furquan@google.com Gerrit-Attention: Kangheui Won khwon@chromium.org Gerrit-Attention: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Gerrit-Attention: chris wang Chris.Wang@amd.com Gerrit-Comment-Date: Mon, 25 Jan 2021 05:21:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Patrick Georgi (Code Review)

25 Jan 25 Jan

1:11 a.m.

New subject: Change in coreboot[master]: mb/google/zork: adjust the eDP panel power sequence

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48865 )

Change subject: mb/google/zork: adjust the eDP panel power sequence ......................................................................

mb/google/zork: adjust the eDP panel power sequence

set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight on and vary backlight.

BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on dalboz

Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-)

Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index ddcaf53..c3afe13 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -26,6 +26,18 @@ # eDP phy tuning settings register "dp_phy_override" = "ENABLE_EDP_TUNINGSET"

+ # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, + # and "0" as default value + register "edp_pwr_adjust_enable" = "1" + register "pwron_digon_to_de" = "0" + register "pwron_de_to_varybl" = "0" + register "pwrdown_varybloff_to_de" = "0" + register "pwrdown_de_to_digoff" = "0" + register "pwroff_delay" = "0" + register "pwron_varybl_to_blon" = "5" + register "pwrdown_bloff_to_varybloff" = "5" + register "min_allowed_bl_level" = "0" + register "edp_tuningset" = "{ .dp_vs_pemph_level = 0x0, .deemph_6db4 = 0x004b,

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participants (6)

build bot (Jenkins) (Code Review)
chris wang (Code Review)
EricR Lai (Code Review)
Nikolai Vyssotski (Code Review)
Patrick Georgi (Code Review)
Paul Menzel (Code Review)