[XS] Change in coreboot[main]: soc/intel/common/block/lpc: Support IBL eSPI

[Shuo Liu (Code Review)]

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84309?usp=email )

Change subject: soc/intel/common/block/lpc: Support IBL eSPI
......................................................................

soc/intel/common/block/lpc: Support IBL eSPI

IBL eSPI should be correctly configured by LPC driver so that console
input is usable.

Change-Id: I77cc6dd67b36035974e7f268d32b8473e8d83483
Signed-off-by: Shuo Liu 
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/lpc/lpc.c
2 files changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/84309/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 5308052..bed671c 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3120,6 +3120,7 @@
 #define PCI_DID_INTEL_ADP_M_N_ESPI_30			0x549e
 #define PCI_DID_INTEL_ADP_M_N_ESPI_31			0x549f
 #define PCI_DID_INTEL_SPR_ESPI_1			0x1b80
+#define PCI_DID_INTEL_IBL_ESPI_0			0x5795
 #define PCI_DID_INTEL_MTL_ESPI_0			0x7e00
 #define PCI_DID_INTEL_MTL_ESPI_1			0x7e01
 #define PCI_DID_INTEL_MTL_ESPI_2			0x7e02
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index ef14914..3c02ab9 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -333,6 +333,7 @@
    PCI_DID_INTEL_CMP_H_LPC_H470,
    PCI_DID_INTEL_CMP_H_LPC_Z490,
    PCI_DID_INTEL_CMP_H_LPC_Q470,
+	PCI_DID_INTEL_SNR_LPC,
    PCI_DID_INTEL_TGP_ESPI_0,
    PCI_DID_INTEL_TGP_SUPER_U_ESPI,
    PCI_DID_INTEL_TGP_PREMIUM_U_ESPI,
@@ -447,7 +448,7 @@
    PCI_DID_INTEL_ADP_M_N_ESPI_30,
    PCI_DID_INTEL_ADP_M_N_ESPI_31,
    PCI_DID_INTEL_SPR_ESPI_1,
-	PCI_DID_INTEL_SNR_LPC,
+	PCI_DID_INTEL_IBL_ESPI_0,
    0
 };