[XL] Change in coreboot[master]: New port for Lenovo L420 laptop (bump from v4.18 to master).
Nicolas Provost has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75992?usp=email )
Change subject: New port for Lenovo L420 laptop (bump from v4.18 to master). ......................................................................
New port for Lenovo L420 laptop (bump from v4.18 to master).
Change-Id: I0e46810b80af72c608679235585ec8d5a98d48ac Signed-off-by: Nicolas Provost dev@npsoft.fr --- A src/mainboard/lenovo/l420/Kconfig A src/mainboard/lenovo/l420/Kconfig.name A src/mainboard/lenovo/l420/Makefile.inc A src/mainboard/lenovo/l420/acpi/ec.asl A src/mainboard/lenovo/l420/acpi/platform.asl A src/mainboard/lenovo/l420/acpi/superio.asl A src/mainboard/lenovo/l420/acpi_tables.c A src/mainboard/lenovo/l420/board_info.txt A src/mainboard/lenovo/l420/cmos.default A src/mainboard/lenovo/l420/cmos.layout A src/mainboard/lenovo/l420/data.vbt A src/mainboard/lenovo/l420/devicetree.cb A src/mainboard/lenovo/l420/dsdt.asl A src/mainboard/lenovo/l420/early_init.c A src/mainboard/lenovo/l420/gma-mainboard.ads A src/mainboard/lenovo/l420/gpio.c A src/mainboard/lenovo/l420/hda_verb.c A src/mainboard/lenovo/l420/mainboard.c A src/mainboard/lenovo/l420/seabios.config A src/mainboard/lenovo/l420/smihandler.c A src/mainboard/lenovo/l420/status.txt 21 files changed, 1,110 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/75992/1
diff --git a/src/mainboard/lenovo/l420/Kconfig b/src/mainboard/lenovo/l420/Kconfig new file mode 100644 index 0000000..680d57b --- /dev/null +++ b/src/mainboard/lenovo/l420/Kconfig @@ -0,0 +1,81 @@ +if BOARD_LENOVO_L420 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_BD82X6X + select EC_LENOVO_H8 + select EC_ACPI + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_INT15 + select TPM + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_PANEL_1_ON_LVDS + select INTEL_GMA_HAVE_VBT + + # Workaround for EC/KBC. + select SERIRQ_CONTINUOUS_MODE + + # Realtek 8168 + select REALTEK_8168_RESET + +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + +config MAINBOARD_DIR + default "lenovo/l420" + +config MAINBOARD_PART_NUMBER + default "ThinkPad L420" + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config VGA_BIOS_ID + string + default "8086,0106" + +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0017" + +config THINKPADEC_HKEY_EISAID + default "LEN0068" + +config WARNINGS_ARE_ERRORS + default n + +config PAYLOAD_CONFIGFILE + default "$(CURDIR)/src/mainboard/$(CONFIG_MAINBOARD_DIR)/seabios.config" if PAYLOAD_SEABIOS + +endif # BOARD_LENOVO_L420 diff --git a/src/mainboard/lenovo/l420/Kconfig.name b/src/mainboard/lenovo/l420/Kconfig.name new file mode 100644 index 0000000..5dfc348 --- /dev/null +++ b/src/mainboard/lenovo/l420/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_L420 + bool "ThinkPad L420" diff --git a/src/mainboard/lenovo/l420/Makefile.inc b/src/mainboard/lenovo/l420/Makefile.inc new file mode 100644 index 0000000..eef814f --- /dev/null +++ b/src/mainboard/lenovo/l420/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c + diff --git a/src/mainboard/lenovo/l420/acpi/ec.asl b/src/mainboard/lenovo/l420/acpi/ec.asl new file mode 100644 index 0000000..0e576b1 --- /dev/null +++ b/src/mainboard/lenovo/l420/acpi/ec.asl @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/l420/acpi/platform.asl b/src/mainboard/lenovo/l420/acpi/platform.asl new file mode 100644 index 0000000..c4becaf --- /dev/null +++ b/src/mainboard/lenovo/l420/acpi/platform.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + _SB.PCI0.LPCB.EC.MUTE(1) + _SB.PCI0.LPCB.EC.USBP(0) + _SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + _TZ.MEB1 = 0 + _TZ.MEB2 = 0 + + /* Wake the HKEY to init BT/WWAN */ + _SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + + /* Not implemented. */ + Return(Package(){0,0}) +} diff --git a/src/mainboard/lenovo/l420/acpi/superio.asl b/src/mainboard/lenovo/l420/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/lenovo/l420/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/l420/acpi_tables.c b/src/mainboard/lenovo/l420/acpi_tables.c new file mode 100644 index 0000000..36d3e85 --- /dev/null +++ b/src/mainboard/lenovo/l420/acpi_tables.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/l420/board_info.txt b/src/mainboard/lenovo/l420/board_info.txt new file mode 100644 index 0000000..c0f04ca --- /dev/null +++ b/src/mainboard/lenovo/l420/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/lenovo/l420/cmos.default b/src/mainboard/lenovo/l420/cmos.default new file mode 100644 index 0000000..8244071 --- /dev/null +++ b/src/mainboard/lenovo/l420/cmos.default @@ -0,0 +1,17 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hybrid_graphics_mode=Integrated Only +usb_always_on=Disable +me_state=Normal diff --git a/src/mainboard/lenovo/l420/cmos.layout b/src/mainboard/lenovo/l420/cmos.layout new file mode 100644 index 0000000..daf569c --- /dev/null +++ b/src/mainboard/lenovo/l420/cmos.layout @@ -0,0 +1,108 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +421 1 e 9 sata_mode +422 2 e 13 usb_always_on + +# coreboot config options: ME +424 1 e 14 me_state +425 2 h 0 me_state_prev + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode + +440 8 h 0 volume + +# VBOOT +448 128 r 0 vbnv + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only +14 0 Normal +14 1 Disabled + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/lenovo/l420/data.vbt b/src/mainboard/lenovo/l420/data.vbt new file mode 100644 index 0000000..4db2694 --- /dev/null +++ b/src/mainboard/lenovo/l420/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/l420/devicetree.cb b/src/mainboard/lenovo/l420/devicetree.cb new file mode 100644 index 0000000..a3243a4 --- /dev/null +++ b/src/mainboard/lenovo/l420/devicetree.cb @@ -0,0 +1,147 @@ +# PCIe map: +# 0 -> x +# 1 -> WLAN +# 2 -> SD/MMC reader +# 3 -> Express Card +# 4 -> x +# 5 -> LAN RTL8111 +# 6 -> x +# 7 -> x +# +# NP: +# 0C31 -> TPM +# 0C09 -> IT8518 (EC) +# 0C14 -> WMI +# 0C0A -> battery control +# IBM0068 -> ThinkPad button +# INT3f0d -> Interphase Corporation (?) +# 0C0C -> Power button +# 0C0D -> Lid device +# 0C0E -> Sleep button +# 0C02 +# 0F13 -> PS2 mouse (touchpad) +# 0B00 -> RTC +# LEN0017 -> touchpad +# 0303 -> keyboard +# 0C04 +# +chip northbridge/intel/sandybridge + # IGD Displays (spread spectrum on) + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms + register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms + register "gpu_panel_power_backlight_on_delay" = "2500" # T3: 200ms + register "gpu_panel_power_backlight_off_delay" = "2500" # T4: 200ms + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" + + device domain 0 on + subsystemid 0x17aa 0x21dd inherit + + device pci 00.0 on end # host bridge + device pci 01.0 off end # host bridge for discrete graphic + device pci 02.0 on end # Integrated Graphics Controller + device pci 04.0 off end # Signal Processing Controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + # IT8518 SIO_EXT_SMI# -> GPIO1 + # IT8518 SIO_EXT_SCI# -> GPIO6 + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "1" + register "gpi6_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & + # 3 (eSATA) & 4 (dock) + register "sata_port_map" = "0x1f" + + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + # I/O default values: 0x480 (0x80) for GPIOBASE, + # 0x500 (PMBASE), 0x560 (TCOBASE) + # EC = IT8518 60h/64h (KBC) + + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + # device specific SPI configuration + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + + device pci 1a.0 on end # USB Enhanced Host Controller #2 + + device pci 1b.0 on end # High Definition Audio Controller + + device pci 1c.0 off end # PCIe Port + + device pci 1c.1 on end # PCIe Port WLAN + + device pci 1c.2 on end # PCIe Port SD/MMC reader + + device pci 1c.3 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port Express Card + + device pci 1c.4 off end # PCIe Port + + device pci 1c.5 on # PCIe Port #6 Realtek Gigabit 8111 + chip drivers/net + device pci 00.0 on end + end + end + + device pci 1c.6 off end # PCIe Port #7 + + device pci 1c.7 off end # PCIe Port #8 + + device pci 1d.0 on end # USB Enhanced Host Controller #1 + + device pci 1e.0 off end # PCI bridge + + device pci 1f.0 on # ISA LPC bridge + device pnp 0c09.0 on end # IT8518 EC + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end # LPC Controller + + device pci 1f.2 on end # 6 port SATA AHCI Controller (1st) + + device pci 1f.3 on # SMBus + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus Controller + + device pci 1f.5 off end # SATA Controller 2 + + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/l420/dsdt.asl b/src/mainboard/lenovo/l420/dsdt.asl new file mode 100644 index 0000000..f574eca --- /dev/null +++ b/src/mainboard/lenovo/l420/dsdt.asl @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define THINKPAD_EC_GPE 0x16 +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +#define EC_SCI_GPI 6 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20230620 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include "acpi/platform.asl" + + // global NVS and variables + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} + diff --git a/src/mainboard/lenovo/l420/early_init.c b/src/mainboard/lenovo/l420/early_init.c new file mode 100644 index 0000000..2b73335 --- /dev/null +++ b/src/mainboard/lenovo/l420/early_init.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <device/device.h> + +/* + USB map: + ECHCI1: + 0 -> USB0 eSata Combo + 1 -> USB1 (AUO3), OC0 + 2 -> Express Card + 3 -> Camera + 4 -> WLAN + 5 -> WWAN + 6 -> x + ECHCI2: + 7 -> x + 8 -> USB3, OC4 + 9 -> USB2, OC4 + 10 -> Fingerprint reader + 11 -> Dock USB + 12 -> x (Reserved) + 13 -> BlueTooth +*/ +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, /* 0 */ + { 1, 1, 0 }, /* 1 OC0 */ + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 0, 0, -1 }, /* 6 off */ + { 0, 0, -1 }, /* 7 off */ + { 1, 1, 4 }, /* 8 USB3 OC4 */ + { 1, 1, 4 }, /* 9 USB2 OC4 */ + { 1, 0, -1 }, + { 1, 0, -1 }, + { 0, 0, -1 }, /* 12 off */ + { 1, 0, -1 }, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} + +void mainboard_early_init(int s3resume) +{ +} + diff --git a/src/mainboard/lenovo/l420/gma-mainboard.ads b/src/mainboard/lenovo/l420/gma-mainboard.ads new file mode 100644 index 0000000..3df1e37 --- /dev/null +++ b/src/mainboard/lenovo/l420/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/l420/gpio.c b/src/mainboard/lenovo/l420/gpio.c new file mode 100644 index 0000000..9c05890 --- /dev/null +++ b/src/mainboard/lenovo/l420/gpio.c @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, // + .gpio1 = GPIO_MODE_GPIO, // -EC_SMI - input + .gpio2 = GPIO_MODE_GPIO, // DOCKID0 - input + .gpio3 = GPIO_MODE_GPIO, // DOCKID1 - input + .gpio4 = GPIO_MODE_GPIO, // DOCKID2 - input + .gpio5 = GPIO_MODE_GPIO, // INTH# + .gpio6 = GPIO_MODE_GPIO, // EC_SCI - input + .gpio7 = GPIO_MODE_GPIO, // EXPRCRD_PWREN# - input + .gpio8 = GPIO_MODE_GPIO, // + .gpio9 = GPIO_MODE_NATIVE, // OC5# - input + .gpio10 = GPIO_MODE_NATIVE, // OC6# - pullup + .gpio11 = GPIO_MODE_NATIVE, // SMBALERT# pullup + .gpio12 = GPIO_MODE_GPIO, // GPIO12 + .gpio13 = GPIO_MODE_NATIVE, // HDA_DOCK_RST# + .gpio14 = GPIO_MODE_NATIVE, // OC7# - input + .gpio15 = GPIO_MODE_GPIO, // input - 3V_S5 + .gpio16 = GPIO_MODE_GPIO, // GPIO16 + .gpio17 = GPIO_MODE_GPIO, // DGFX_PW RGD - input + .gpio18 = GPIO_MODE_NATIVE, // PCIE_CLKREQ_WLAN# - input + .gpio19 = GPIO_MODE_GPIO, // BBS_BIT0 + .gpio20 = GPIO_MODE_NATIVE, // PCIE_CLKRQ_CARD# - pullup + .gpio21 = GPIO_MODE_GPIO, // DGT_STOP# - input + .gpio22 = GPIO_MODE_GPIO, // MODEL_ID0 - input + .gpio23 = GPIO_MODE_GPIO, // LCD_BK_OFF - output + .gpio24 = GPIO_MODE_GPIO, // pullup + .gpio25 = GPIO_MODE_NATIVE, // PCIE_CLKREQ_NEW# - input + .gpio26 = GPIO_MODE_NATIVE, // PCIECLKRQ4# - pullup + .gpio27 = GPIO_MODE_GPIO, // -MSATA_DTCT - input + .gpio28 = GPIO_MODE_GPIO, // PLL_ODVR_EN - output + .gpio29 = GPIO_MODE_NATIVE, // PCH_SLP_LAN# + .gpio30 = GPIO_MODE_NATIVE, // SUSPWRDNACK - output + .gpio31 = GPIO_MODE_NATIVE, // ACPRESENT - input +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, // LCD_BK_OFF + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, // LCD_BK_OFF + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + /*.gpio1 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio13 = GPIO_INVERT,*/ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +// .gpio18 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +// .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, // CLKRUN# - in/out + .gpio33 = GPIO_MODE_GPIO, // GPIO33 (HDA_DOCK_EN#) + .gpio34 = GPIO_MODE_GPIO, // GPIO34 + .gpio35 = GPIO_MODE_GPIO, // BT_ON - output + .gpio36 = GPIO_MODE_GPIO, // BOARD_ID0 - input + .gpio37 = GPIO_MODE_GPIO, // BOARD_ID1 - input + .gpio38 = GPIO_MODE_GPIO, // BOARD_ID2 - input + .gpio39 = GPIO_MODE_GPIO, // BOARD_ID3 - input + .gpio40 = GPIO_MODE_NATIVE, // OC1# - input + .gpio41 = GPIO_MODE_NATIVE, // OC2# - input + .gpio42 = GPIO_MODE_NATIVE, // OC3# - input + .gpio43 = GPIO_MODE_NATIVE, // OC4# - input + .gpio44 = GPIO_MODE_NATIVE, // PCI_CLKREQ_LAN# - input + .gpio45 = GPIO_MODE_NATIVE, // PCIECLKRQ6# - input + .gpio46 = GPIO_MODE_NATIVE, // PCIECLKRQ7# - pullup + .gpio47 = GPIO_MODE_NATIVE, // PEG_A_CLKRQ# - input + .gpio48 = GPIO_MODE_GPIO, // pullup gpio + .gpio49 = GPIO_MODE_GPIO, // pullup gpio + .gpio50 = GPIO_MODE_NATIVE, // PCI_REQ1# + .gpio51 = GPIO_MODE_GPIO, // BBS_BIT1 - output + .gpio52 = GPIO_MODE_NATIVE, // PCI_REQ2# + .gpio53 = GPIO_MODE_GPIO, // PWM_SELECT# + .gpio54 = GPIO_MODE_GPIO, // BT_DET# - input + .gpio55 = GPIO_MODE_NATIVE, // PCI_GNT3# + .gpio56 = GPIO_MODE_NATIVE, // PEG_B_CLKRQ# - pullup + .gpio57 = GPIO_MODE_GPIO, // gpio + .gpio58 = GPIO_MODE_NATIVE, // SML1CLK - - output + .gpio59 = GPIO_MODE_NATIVE, // OC0# - pullup + .gpio60 = GPIO_MODE_GPIO, // DRAMRST_CNTRL_PCH - input + .gpio61 = GPIO_MODE_GPIO, // LPCPD# - output + .gpio62 = GPIO_MODE_NATIVE, // SUSCLK - output + .gpio63 = GPIO_MODE_NATIVE, // SLP_S5 - output +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, // CLK_FLEX0 + .gpio65 = GPIO_MODE_NATIVE, // CLK_FLEX1 + .gpio66 = GPIO_MODE_NATIVE, // CLK_FLEX2 + .gpio67 = GPIO_MODE_NATIVE, // CLK_FLEX3 + .gpio68 = GPIO_MODE_GPIO, // WWAN_DTCT# - input + .gpio69 = GPIO_MODE_GPIO, // pulldown + .gpio70 = GPIO_MODE_GPIO, // WLAN_OFF# - output, pullup + .gpio71 = GPIO_MODE_GPIO, // WWAN_OFF# - output + .gpio72 = GPIO_MODE_NATIVE, // BATLOW# - input + .gpio73 = GPIO_MODE_NATIVE, // PCIE_CLKREQ0# + .gpio74 = GPIO_MODE_NATIVE, // SML1ALERT# + .gpio75 = GPIO_MODE_NATIVE, // SML1DATA - EC_SDA2 - i/o +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + .blink = &pch_gpio_set1_blink, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/lenovo/l420/hda_verb.c b/src/mainboard/lenovo/l420/hda_verb.c new file mode 100644 index 0000000..0c19c91 --- /dev/null +++ b/src/mainboard/lenovo/l420/hda_verb.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ + 0x17aa21ce, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21dd), + AZALIA_PIN_CFG(0, 0x19, 0x04211040), + AZALIA_PIN_CFG(0, 0x1a, 0x61a19050), + AZALIA_PIN_CFG(0, 0x1b, 0x04a11060), + AZALIA_PIN_CFG(0, 0x1c, 0x6121401f), + AZALIA_PIN_CFG(0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1f, 0x90170110), + AZALIA_PIN_CFG(0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x23, 0x90a60170), + + /* Misc entries */ + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ + + /* --- Codec #3 --- */ + 0x80862805, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/l420/mainboard.c b/src/mainboard/lenovo/l420/mainboard.c new file mode 100644 index 0000000..f98b4b1 --- /dev/null +++ b/src/mainboard/lenovo/l420/mainboard.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/pci_ops.h> +#include <drivers/intel/gma/int15.h> +#include <acpi/acpi.h> +#include <southbridge/intel/bd82x6x/pch.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/lenovo/l420/seabios.config b/src/mainboard/lenovo/l420/seabios.config new file mode 100644 index 0000000..ac62482 --- /dev/null +++ b/src/mainboard/lenovo/l420/seabios.config @@ -0,0 +1,98 @@ +# +# Automatically generated file; DO NOT EDIT. +# SeaBIOS Configuration +# + +# +# General Features +# +CONFIG_COREBOOT=y +# CONFIG_QEMU is not set +# CONFIG_CSM is not set +# CONFIG_QEMU_HARDWARE is not set +CONFIG_THREADS=y +CONFIG_RELOCATE_INIT=y +CONFIG_BOOTMENU=y +# CONFIG_BOOTSPLASH is not set +CONFIG_BOOTORDER=y +CONFIG_HOST_BIOS_GEOMETRY=y +CONFIG_COREBOOT_FLASH=y +CONFIG_LZMA=y +CONFIG_CBFS_LOCATION=0 +CONFIG_MULTIBOOT=y +CONFIG_ENTRY_EXTRASTACK=y +CONFIG_MALLOC_UPPERMEMORY=y +CONFIG_ROM_SIZE=0 + +# +# Hardware support +# +CONFIG_ATA=y +# CONFIG_ATA_DMA is not set +# CONFIG_ATA_PIO32 is not set +CONFIG_AHCI=y +CONFIG_SDCARD=y +# CONFIG_MEGASAS is not set +# CONFIG_FLOPPY is not set +# CONFIG_FLASH_FLOPPY is not set +# CONFIG_NVME is not set +CONFIG_PS2PORT=y +CONFIG_USB=y +CONFIG_USB_UHCI=y +CONFIG_USB_OHCI=y +CONFIG_USB_EHCI=y +CONFIG_USB_XHCI=y +CONFIG_USB_MSC=y +CONFIG_USB_UAS=y +CONFIG_USB_HUB=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_MOUSE=y +CONFIG_SERIAL=y +CONFIG_SERCON=y +CONFIG_LPT=y +CONFIG_RTC_TIMER=y +CONFIG_HARDWARE_IRQ=y +CONFIG_PMTIMER=y +CONFIG_TSC_TIMER=y + +# +# BIOS interfaces +# +CONFIG_DRIVES=y +CONFIG_CDROM_BOOT=y +CONFIG_CDROM_EMU=y +CONFIG_PCIBIOS=y +CONFIG_APMBIOS=y +CONFIG_PNPBIOS=y +CONFIG_OPTIONROMS=y +CONFIG_PMM=y +CONFIG_BOOT=y +CONFIG_KEYBOARD=y +CONFIG_KBD_CALL_INT15_4F=y +CONFIG_MOUSE=y +CONFIG_S3_RESUME=y +CONFIG_VGAHOOKS=y +# CONFIG_DISABLE_A20 is not set +CONFIG_TCGBIOS=y + +# +# VGA ROM +# +# CONFIG_NO_VGABIOS is not set +# CONFIG_VGA_GEODEGX2 is not set +# CONFIG_VGA_GEODELX is not set +CONFIG_VGA_COREBOOT=y +CONFIG_BUILD_VGABIOS=y +CONFIG_VGA_EMULATE_TEXT=y +CONFIG_VGA_FIXUP_ASM=y +CONFIG_VGA_ALLOCATE_EXTRA_STACK=y +CONFIG_VGA_EXTRA_STACK_SIZE=512 +CONFIG_VGA_VBE=y + +# +# Debugging +# +CONFIG_DEBUG_LEVEL=1 +# CONFIG_DEBUG_SERIAL is not set +# CONFIG_DEBUG_SERIAL_MMIO is not set +CONFIG_DEBUG_COREBOOT=y diff --git a/src/mainboard/lenovo/l420/smihandler.c b/src/mainboard/lenovo/l420/smihandler.c new file mode 100644 index 0000000..41fd1fb --- /dev/null +++ b/src/mainboard/lenovo/l420/smihandler.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> + +#define GPE_EC_SCI 6 + +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %#02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} + diff --git a/src/mainboard/lenovo/l420/status.txt b/src/mainboard/lenovo/l420/status.txt new file mode 100644 index 0000000..f6a0c4f --- /dev/null +++ b/src/mainboard/lenovo/l420/status.txt @@ -0,0 +1,36 @@ +L420 hardware status +==================== + +Chipset: C200/HM65 (Cougar Point, Hudson River, cpu 0x206ax). + +Component | Status | Date | Remark +-------------|--------------|--------|----------------------------------------- +ACPI | OK |23/06/20| Fan always on ? +LCD | OK |22/11/20| +Video | OK |22/11/20| Tested on LVDS panel. +Memory | OK |23/06/21| Tested, 8 GB (may work with 16GB). +CPU | OK |22/11/20| 4 cores +LAN | OK |22/11/20| Realtek 8111B +TPM | OK |22/11/20| +Keyboard | OK |22/11/20| +Touchpad | Should work |23/06/20| (present in device tree) +Trackpoint | Should work |23/06/20| (present in device tree) +Audio | OK |22/11/20| +WLAN | Should work | | (present in device tree) +WWAN | Should work | | (present in device tree) +SATA | OK |22/11/20| +eSATA | ? | | (present in device tree) +Fingerprint | should work |22/11/20| (USB) +SD/MMC | ? | | +USB0 | should work |22/11/20| (eSATA combo in device tree) +USB1 | should work |22/11/20| (yellow port, in device tree) +USB2 | OK |22/11/20| +USB3 | OK |22/11/20| +ExpressCard | OK |23/06/21| +Suspend | ? | | +Battery | OK |22/11/20| Charge ok. Status report to do (ACPI). + +ChangeLog: +22/11/20: initial port to v4.18 +23/06/21: adapted to master +
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Nicolas Provost (Code Review)