New patch to review for coreboot: soc/glk: Put LPSS in D3 The dummy read of PMCSR register is needed for this

[Hannah Williams]

Hannah Williams ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17825

-gerrit

commit 98d44ac922367150b5998841d399b4f678b7b23c
Author: Hannah Williams 
Date:   Wed Nov 9 19:30:58 2016 -0800

soc/glk: Put LPSS in D3
    The dummy read of PMCSR register is needed for this

Change-Id: Ibdf42ad0d3f10d9be38231b91be69e4bdf7d2cc8
    Signed-off-by: Hannah Williams 
---
 src/soc/intel/glk/acpi/lpss.asl | 42 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/src/soc/intel/glk/acpi/lpss.asl b/src/soc/intel/glk/acpi/lpss.asl
index ab97374..2e6867b 100644
--- a/src/soc/intel/glk/acpi/lpss.asl
+++ b/src/soc/intel/glk/acpi/lpss.asl
@@ -17,52 +17,78 @@

scope (_SB.PCI0) {

+	Method(LPD3, 0, Serialized) {
+		OperationRegion (PMCS, PCI_Config, 0x84, 0x4)
+		Field (PMCS, WordAcc, NoLock, Preserve) {
+			PMSR, 32,   // 0x84, PMCSR - Power Management Control and Status
+		}
+		// dummy read PMCSR
+		Store (PMSR, Local0)
+		And (Local0, 1, Local0) // Dummy operation on Local0
+	}
+
    /* LPIO1 PWM */
    Device(PWM) {
    	Name (_ADR, 0x001A0000)
    	Name (_DDN, "Intel(R) PWM Controller")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO1 HS-UART #1 */
    Device(URT1) {
    	Name (_ADR, 0x00180000)
    	Name (_DDN, "Intel(R) HS-UART Controller #1")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO1 HS-UART #2 */
    Device(URT2) {
    	Name (_ADR, 0x00180001)
    	Name (_DDN, "Intel(R) HS-UART Controller #2")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO1 HS-UART #3 */
    Device(URT3) {
    	Name (_ADR, 0x00180002)
    	Name (_DDN, "Intel(R) HS-UART Controller #3")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO1 HS-UART #4 */
    Device(URT4) {
    	Name (_ADR, 0x00180003)
    	Name (_DDN, "Intel(R) HS-UART Controller #4")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO1 SPI */
    Device(SPI1) {
    	Name (_ADR, 0x00190000)
    	Name (_DDN, "Intel(R) SPI Controller #1")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO1 SPI #2 */
    Device(SPI2) {
    	Name (_ADR, 0x00190001)
    	Name (_DDN, "Intel(R) SPI Controller #2")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO1 SPI #3 */
    Device(SPI3) {
    	Name (_ADR, 0x00190002)
    	Name (_DDN, "Intel(R) SPI Controller #3")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

@@ -70,47 +96,63 @@ scope (_SB.PCI0) {
    Device(I2C0) {
    	Name (_ADR, 0x00160000)
    	Name (_DDN, "Intel(R) I2C Controller #0")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO2 I2C #1 */
    Device(I2C1) {
    	Name (_ADR, 0x00160001)
    	Name (_DDN, "Intel(R) I2C Controller #1")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO2 I2C #2 */
    Device(I2C2) {
    	Name (_ADR, 0x00160002)
    	Name (_DDN, "Intel(R) I2C Controller #2")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO2 I2C #3 */
    Device(I2C3) {
    	Name (_ADR, 0x00160003)
    	Name (_DDN, "Intel(R) I2C Controller #3")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO2 I2C #4 */
    Device(I2C4) {
    	Name (_ADR, 0x00170000)
    	Name (_DDN, "Intel(R) I2C Controller #4")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO2 I2C #5 */
    Device(I2C5) {
    	Name (_ADR, 0x00170001)
    	Name (_DDN, "Intel(R) I2C Controller #5")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO2 I2C #6 */
    Device(I2C6) {
    	Name (_ADR, 0x00170002)
    	Name (_DDN, "Intel(R) I2C Controller #6")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }

/* LPIO2 I2C #7 */
    Device(I2C7) {
    	Name (_ADR, 0x00170003)
    	Name (_DDN, "Intel(R) I2C Controller #7")
+		Method (_PS0) { }
+                Method (_PS3) {LPD3 ()}
    }
 }