Patch set updated for coreboot: 18ca0bd pistachio: add timer frequency for SOC; correct platform ID

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9193

-gerrit

commit 18ca0bdb5ea40c509c03ec78f97a08ea5942a95b
Author: Ionela Voinescu 
Date:   Mon Jan 19 02:39:18 2015 +0000

pistachio: add timer frequency for SOC; correct platform ID

Corrected platform ID and added timer frequency for SOC.
    The timer frequency is half the CPU frequency.

BUG=chrome-os-partner:31438
    TEST=tested on Pistachio bring up board; behaves as expected.
    BRANCH=none

Change-Id: If7e03232106b52f2522fc7da586bdaf95f5eefec
    Signed-off-by: Stefan Reinauer 
    Original-Commit-Id: d94789950d5300bbe5defbf529480d8d545e743e
    Original-Change-Id: I1187e4b5280eaf796777d882a2e154e2808e9e37
    Original-Signed-off-by: Ionela Voinescu 
    Original-Reviewed-on: https://chromium-review.googlesource.com/241426
    Original-Reviewed-by: David Hendricks 
---
 src/soc/imgtec/pistachio/include/soc/cpu.h | 12 ++++++++----
 src/soc/imgtec/pistachio/monotonic_timer.c | 19 ++++++++++++++++---
 2 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h
index 72775b5..8995219 100644
--- a/src/soc/imgtec/pistachio/include/soc/cpu.h
+++ b/src/soc/imgtec/pistachio/include/soc/cpu.h
@@ -18,14 +18,18 @@
 #ifndef __SOC_IMGTEC_DANUBE_CPU_H__
 #define __SOC_IMGTEC_DANUBE_CPU_H__

+#include <arch/io.h>
+
 #define IMG_SPIM0_BASE_ADDRESS	0xB8100F00
 #define IMG_SPIM1_BASE_ADDRESS	0xB8101000

/*
- * Reading at this address allows to identify the platform the code is running
- * on.
+ * This register holds the FPGA image version
+ * If we're not working on the FPGA this will be 0
  */
-#define IMG_PLATFORM_ID()	(*((unsigned *)0xB8149060))
-#define IMG_PLATFORM_ID_SILICON 0xF00D0006
+#define PRIMARY_FPGA_VERSION		0xB8149060
+#define IMG_PLATFORM_ID()		read32(PRIMARY_FPGA_VERSION)
+#define IMG_PLATFORM_ID_FPGA		0xD1400003 /* Last FPGA image */
+#define IMG_PLATFORM_ID_SILICON		0

#endif
diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c
index 99c147b..c2408b0 100644
--- a/src/soc/imgtec/pistachio/monotonic_timer.c
+++ b/src/soc/imgtec/pistachio/monotonic_timer.c
@@ -23,6 +23,9 @@
 #include <arch/cpu.h>
 #include <soc/cpu.h>

+#define PISTACHIO_CLOCK_SWITCH		0xB8144200
+#define MIPS_EXTERN_PLL_BYPASS_MASK	0x00000002
+
 static int get_count_mhz_freq(void)
 {
    static unsigned count_mhz_freq;
@@ -30,10 +33,20 @@ static int get_count_mhz_freq(void)
    if (!count_mhz_freq) {
    	if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
    		count_mhz_freq = 25; /* FPGA board */
-			/*
-			 * Will need some means of finding out the counter
-			 * frequency on a real SOC
+		else {
+			/* If MIPS PLL external bypass bit is set, it means
+			 * that the MIPS PLL is already set up to work at a
+			 * frequency of 550 MHz; otherwise, the crystal is
+			 * used with a frequency of 52 MHz
    		 */
+			if (read32(PISTACHIO_CLOCK_SWITCH) &
+				MIPS_EXTERN_PLL_BYPASS_MASK)
+				/* Half MIPS PLL freq. */
+				count_mhz_freq = 275;
+			else
+				/* Half Xtal freq. */
+				count_mhz_freq = 26;
+		}
    }
    return count_mhz_freq;
 }