Change in coreboot[master]: soc/intel/tigerlake: Invoke PCIe root port swapping

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43850 )

Change subject: soc/intel/tigerlake: Invoke PCIe root port swapping
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43850/1/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.c:

https://review.coreboot.org/c/coreboot/+/43850/1/src/soc/intel/tigerlake/chi... 
PS1, Line 21: PCH_DEV_SLOT_PCIE
> There also seems to be PCH_DEV_SLOT_PCIE_1 with 4 functions. […]

In JSL, we only have 8 PCIe root ports and hence added only those ports. TGL seems to have more  - 12 root ports. So as Duncan mentioned, PCH_DEV_SLOT_PCIE_1 needs to be included. I can see them listed in the devicetree and also some of them enabled in the devicetree.