Change in coreboot[master]: vc/amd/sb800: Fix out of bounds shift

[Paul Menzel (Code Review)]

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51283 )

Change subject: vc/amd/sb800: Fix out of bounds shift
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vc/amd/sb800: Fix out of bounds shift

Fix the two issues below.

SB800: sb_Before_Pci_Init
    shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:49:18
    ubsan: unrecoverable error.

SB800: sb_Before_Pci_Init
    shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:66:18
    ubsan: unrecoverable error.

Found by: UBSAN
Signed-off-by: Paul Menzel

Change-Id: Id42e62d35f59793bad10998f14422ab7fb4fc029
---
M src/vendorcode/amd/cimx/sb800/PCILIB.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/51283/1

diff --git a/src/vendorcode/amd/cimx/sb800/PCILIB.c b/src/vendorcode/amd/cimx/sb800/PCILIB.c
index 01be81a..c34c5b0 100644
--- a/src/vendorcode/amd/cimx/sb800/PCILIB.c
+++ b/src/vendorcode/amd/cimx/sb800/PCILIB.c
@@ -46,7 +46,7 @@
   if ( (UINT16)Address < 0xff ) {
     //Normal Config Access
     UINT32 AddrCf8;
-    AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
+    AddrCf8 = (1U << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
     WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
     ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
   }
@@ -63,7 +63,7 @@
   if ( (UINT16)Address < 0xff ) {
     //Normal Config Access
     UINT32 AddrCf8;
-    AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
+    AddrCf8 = (1U << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
     WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
     WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
   }