Change in coreboot[master]: mb/google/brya/var/craask: Add GPIO table and Fw_config settings

[Tyler Wang (Code Review)]

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63817 )

Change subject: mb/google/brya/var/craask: Add GPIO table and Fw_config settings
......................................................................

mb/google/brya/var/craask: Add GPIO table and Fw_config settings

1. Fill GPIO table for Craask.
2. Disable LTE-related GPIOs based on fw_config

BUG=None
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang 
Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2
---
A src/mainboard/google/brya/variants/craask/Makefile.inc
A src/mainboard/google/brya/variants/craask/fw_config.c
A src/mainboard/google/brya/variants/craask/gpio.c
3 files changed, 83 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63817/1

diff --git a/src/mainboard/google/brya/variants/craask/Makefile.inc b/src/mainboard/google/brya/variants/craask/Makefile.inc
new file mode 100644
index 0000000..17b1254
--- /dev/null
+++ b/src/mainboard/google/brya/variants/craask/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c
new file mode 100644
index 0000000..c475ca3
--- /dev/null
+++ b/src/mainboard/google/brya/variants/craask/fw_config.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+static const struct pad_config lte_disable_pads[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
+	/* D6  : WWAN_EN */
+	PAD_NC(GPP_D6, NONE),
+	/* F12 : WWAN_RST_L */
+	PAD_NC(GPP_F12, NONE),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_NC(GPP_H19, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_NC(GPP_H23, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
+		printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
+		gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c
new file mode 100644
index 0000000..93ae776
--- /dev/null
+++ b/src/mainboard/google/brya/variants/craask/gpio.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* F12 : GSXDOUT ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 1, DEEP),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}