Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation - coreboot-gerrit

18 Nov 2021


      Attention is currently required from: Arthur Heymans, Tim Wawrzynczak, Angel Pons, Patrick Rudolph.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58517 )
Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation
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Patch Set 6:
(1 comment)
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/58517/comment/93cb33e8_a00c23ab 
PS5, Line 48: the hardware of FSP
...
I think it's not FSP's fault. To me, it looks like _PRT just lacks the entry for PEG INT D.
Well this should have FSP configure PIN A,B,C for the 3 PEG functions. It ends up using pin D.
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Gerrit-Project: coreboot
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