[XL] Change in coreboot[main]: nb/via/cx700: Implement raminit

[Nico Huber (Code Review)]

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Change subject: nb/via/cx700: Implement raminit
......................................................................

nb/via/cx700: Implement raminit

This brings the old raminit implementation for CX700 back. It was
removed in commit e99f0390b9b8 (Remove VIA CX700 northbridge sup-
port). The code is mostly unchanged, three minor issues are fixed:

* A shift (>>= 2) was missing when reading tRRD from SPD byte 28.
  The fixed value matches  what the vendor BIOS of a VIA EPIA-EX
  board programs. The code also suggests that we are looking for
  a small value (<= 19 for DDR2-533).

* We allow the board port to specify which clock outputs should
  be enabled now.  This is necessary for the VIA EPIA-EX, which
  needs the ALL_MCLKO setting  (instead of the previously hard-
  coded MCLKO2.

* When programming the DQS output delays, we considered the 1~2
  rank values only for single-rank configurations. Changing the
  `< 2` to `<= 2`  brings us closer to the vendor values on the
  VIA EPIA-EX.

Otherwise a lot of cosmetics changed. Partly because the original
code was to be #included into another C file, but also to satisfy
checkpatch. Also, all the #if'd code was removed (32-bit width
option, ECC, etc.).

Change-Id: Ibc36b4f314cdf47f18c8be0fcb98218c50938e94
Signed-off-by: Nico Huber 
---
M src/cpu/via/c7/Makefile.mk
M src/mainboard/via/epia-ex/devicetree.cb
M src/northbridge/via/cx700/Kconfig
M src/northbridge/via/cx700/Makefile.mk
A src/northbridge/via/cx700/chip.h
A src/northbridge/via/cx700/memmap.c
A src/northbridge/via/cx700/raminit.c
A src/northbridge/via/cx700/raminit.h
A src/northbridge/via/cx700/registers.h
M src/northbridge/via/cx700/romstage.c
10 files changed, 1,800 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/82770/3