[M] Change in coreboot[master]: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74363?usp=email )

Change subject: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2
......................................................................

mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2

Define a CMOS layout for Librem Mini v1/v2 spanning both banks.  The
only setting provided is the automatic power-on setting, which is
implemented by the EC.  This can now be configured in a firmware image
by replacing cmos.default in CBFS.

Since cmos.default is applied early in bootblock, the EC BRAM interface
must now be configured in bootblock, including opening the LPC I/O
range.

Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941
Signed-off-by: Jonathon Hall 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74363
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/purism/librem_cnl/Kconfig
M src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc
A src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c
A src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.default
A src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout
5 files changed, 64 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
index 0c17ec9..ef05a3e 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -15,11 +15,15 @@

config BOARD_PURISM_LIBREM_MINI
    select BOARD_PURISM_BASEBOARD_LIBREM_CNL
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
    select SOC_INTEL_WHISKEYLAKE
    select SUPERIO_ITE_IT8528E

config BOARD_PURISM_LIBREM_MINI_V2
    select BOARD_PURISM_BASEBOARD_LIBREM_CNL
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
    select SOC_INTEL_COMETLAKE_1
    select SUPERIO_ITE_IT8528E

@@ -85,6 +89,12 @@
 config PC_CMOS_BASE_PORT_BANK1
    default 0x360

+config CMOS_LAYOUT_FILE
+	default "src/mainboard/$(MAINBOARDDIR)/variants/librem_mini/cmos.layout"
+
+config CMOS_DEFAULT_FILE
+	default "src/mainboard/$(MAINBOARDDIR)/variants/librem_mini/cmos.default"
+
 endif

config ENABLE_EC_UART1
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc
index 20ff438..874cde1 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc
@@ -2,3 +2,4 @@

all-y += die.c
 smm-y += die.c
+bootblock-y += bootblock.c
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c
new file mode 100644
index 0000000..558815c
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8528e/it8528e.h>
+#include <intelblocks/lpc_lib.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	/*
+	 * Enable the EC BRAM interface, and set bank 1's I/O BAR.
+	 * BRAM on this board uses bank 0 from the PCH and bank 1 from the EC:
+	 *
+	 * - PCH bank 0 is used for the RTC.  Either should work, but the PCH
+	 *   RTC was used historically, and it's preferable not to change this
+	 *   in an update.
+	 * - EC bank 1 contains the automatic-power-on setting, which is useful
+	 *   to use the Mini as an appliance-like server.
+	 *
+	 * cmos.default can be used to configure the automatic power-on setting
+	 * in firmware.  We have to set up the BRAM interface in bootblock,
+	 * because cmos.default is applied early in bootblock.
+	 */
+	const pnp_devfn_t ec_rtct_dev = PNP_DEV(0x2E, IT8528E_RTCT);
+	pnp_enter_conf_state(ec_rtct_dev);
+	pnp_set_logical_device(ec_rtct_dev);
+	pnp_set_enable(ec_rtct_dev, 1);
+	pnp_set_iobase(ec_rtct_dev, 0x62, CONFIG_PC_CMOS_BASE_PORT_BANK1);
+	pnp_exit_conf_state(ec_rtct_dev);
+
+	/* Open the BRAM 1 bank interface on LPC */
+	lpc_open_pmio_window(CONFIG_PC_CMOS_BASE_PORT_BANK1, 2);
+}
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.default b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.default
new file mode 100644
index 0000000..1c414b3
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.default
@@ -0,0 +1 @@
+power_on_after_fail=Disable
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout
new file mode 100644
index 0000000..454ea8b
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout
@@ -0,0 +1,18 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+# start-bit	length	config	config-ID	name
+0		112	r	0		reserved_memory
+1352		8	e	1		power_on_after_fail
+
+enumerations
+#ID	value	text
+1	0	Enable
+1	1	Disable
+
+checksums
+
+# The EC firmware does initialize power_on_after_fail if it is invalid, but it
+# does not have a checksum.  Put a checksum at the end of bank 1.
+checksum 1352 1359 1520