Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59976 )

Change subject: mb/intel/adlrvp: Add support for external clock buffer
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mb/intel/adlrvp: Add support for external clock buffer

ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals.
Out of 7 SRCCLK's 3 will be used for CPU. Rests CLK SRC's are for PCH.
Now if more than 4 PCH devices connected on the platform, external
differential buffer chip needs to be placed at platform level.

A mainboard designer can choose to add an external clock chip,
and select the SRC CLK using CONFIG_INTERNAL_CLKSRC_BUFFER.

CONFIG_INTERNAL_CLKSRC_BUFFER provides the CLKSRC that feed clock to
discrete buffer for further distribution to platform.

Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
2 files changed, 35 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59976/1

diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 6575685..b617d13 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -23,12 +23,14 @@
    select DRIVERS_UART_8250IO
    select MAINBOARD_USES_IFD_EC_REGION
    select SOC_INTEL_ALDERLAKE_PCH_P
+	select GEN3_EXTERNAL_CLOCK_BUFFER

config BOARD_INTEL_ADLRVP_P_EXT_EC
    select BOARD_INTEL_ADLRVP_COMMON
    select DRIVERS_INTEL_PMC
    select INTEL_LPSS_UART_FOR_CONSOLE
    select SOC_INTEL_ALDERLAKE_PCH_P
+	select GEN3_EXTERNAL_CLOCK_BUFFER

config BOARD_INTEL_ADLRVP_P_MCHP
    select BOARD_INTEL_ADLRVP_COMMON
@@ -140,4 +142,19 @@
 config TPM_TIS_ACPI_INTERRUPT
    int
    default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC  # GPE0_DW2_3 (GPP_E3)
+
+config GEN3_EXTERNAL_CLOCK_BUFFER
+	bool
+	default n
+	help
+	  Support external Gen-3 clock chip for ADL-P.
+	  `CONFIG_INTERNAL_CLKSRC_BUFFER` provides feed clock to discrete buffer
+	  for further distribution to platform. SRCCLKREQB[7:9] maps to internal
+	  SRCCLKREQB[6]. If any of them asserted, SRC buffer
+	  `CONFIG_INTERNAL_CLKSRC_BUFFER` gets enabled.
+
+config INTERNAL_CLKSRC_BUFFER
+	depends on GEN3_EXTERNAL_CLOCK_BUFFER
+	int
+	default 6  # CLKSRC 6
 endif
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 34fc04e..43f022c 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -24,6 +24,21 @@
    return spd_index;
 }

+/*
+ * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's
+ * 3 will be used for CPU. Rests CLK SRC's for PCH. Now if more than 4 PCH devices
+ * connected on the platform, external differential buffer chip needs to be placed at
+ * platform level.
+ *
+ * CONFIG_INTERNAL_CLKSRC_BUFFER provides the CLKSRC that feed clock to discrete
+ * buffer for further distribution to platform.
+ */
+static configure_external_clksrc(FSP_M_CONFIG *m_cfg)
+{
+	for (int i = CONFIG_MAX_PCIE_CLOCK_SRC; i < CONFIG_MAX_PCIE_CLOCK_REQ; i++)
+		m_cfg->PcieClkSrcUsage[i] = CONFIG_INTERNAL_CLKSRC_BUFFER;
+}
+
 void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
 {
    const struct mb_cfg *mem_config = variant_memory_params();
@@ -68,4 +83,7 @@
    	die("Unknown board id = 0x%x\n", board_id);
    	break;
    }
+
+	if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER))
+		configure_external_clksrc(m_cfg);
 }