[S] Change in coreboot[main]: intel/common/block: Program the right power_limits_config entry

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85244?usp=email )

Change subject: intel/common/block: Program the right power_limits_config entry
......................................................................

intel/common/block: Program the right power_limits_config entry

When variant_update_cpu_power_limits() programs PL4, it systematically
sets the first entry of the power_limits_config SoC chip data
structure. This approach is problematic because the current SoC SKU
may align with a different data structure entry, introducing
inconsistencies.

This commit introduces the power_limits_index field to the
cpu_tdp_power_limits data structure. This field specifies the specific
power limits entry that should be updated.

All data structures utilized by this function are updated accordingly.

BUG=b:380408956
TEST=Able to retrieve collect 28W power_limit.

Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65
Signed-off-by: Subrata Banik 
Signed-off-by: Jeremy Compostella 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85244
Reviewed-by: Bora Guvendik 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
M src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
M src/mainboard/google/rex/variants/deku/ramstage.c
M src/mainboard/google/rex/variants/screebo/variant.c
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
M src/soc/intel/common/block/include/intelblocks/power_limit.h
M src/soc/intel/common/block/power_limit/power_limit.c
7 files changed, 15 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Bora Guvendik: Looks good to me, approved

diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
index e23fc9a..b1b3b9c 100644
--- a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
@@ -41,6 +41,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_1,
    	.cpu_tdp = 28,
+		.power_limits_index = MTL_P_682_482_CORE,
    	.pl1_min_power = 19000,
    	.pl1_max_power = 28000,
    	.pl2_min_power = 64000,
@@ -50,6 +51,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_3,
    	.cpu_tdp = 28,
+		.power_limits_index = MTL_P_682_482_CORE,
    	.pl1_min_power = 19000,
    	.pl1_max_power = 28000,
    	.pl2_min_power = 64000,
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
index 14fbad2..2b920ad 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
+++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
@@ -15,6 +15,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
    	.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
    	.pl1_min_power = 10000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 57000,
@@ -24,6 +25,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
    	.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
    	.pl1_min_power = 10000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 57000,
@@ -36,6 +38,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
    	.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
    	.pl1_min_power = 10000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 57000,
@@ -45,6 +48,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
    	.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
    	.pl1_min_power = 10000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 57000,
diff --git a/src/mainboard/google/rex/variants/deku/ramstage.c b/src/mainboard/google/rex/variants/deku/ramstage.c
index 0cfcae1..871313c 100644
--- a/src/mainboard/google/rex/variants/deku/ramstage.c
+++ b/src/mainboard/google/rex/variants/deku/ramstage.c
@@ -14,6 +14,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_1,
    	.cpu_tdp = 28,
+		.power_limits_index = MTL_P_682_482_CORE,
    	.pl1_min_power = 19000,
    	.pl1_max_power = 28000,
    	.pl2_min_power = 64000,
@@ -23,6 +24,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_3,
    	.cpu_tdp = 28,
+		.power_limits_index = MTL_P_682_482_CORE,
    	.pl1_min_power = 19000,
    	.pl1_max_power = 28000,
    	.pl2_min_power = 64000,
diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c
index edddd43..00ee19f5 100644
--- a/src/mainboard/google/rex/variants/screebo/variant.c
+++ b/src/mainboard/google/rex/variants/screebo/variant.c
@@ -35,6 +35,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
    	.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
    	.pl1_min_power = 10000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 40000,
@@ -44,6 +45,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
    	.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
    	.pl1_min_power = 10000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 40000,
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
index aee3d88..16f85ba 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

#include <baseboard/variants.h>
+#include <chip.h>
 #include <device/pci_ids.h>
 #include <intelblocks/power_limit.h>

@@ -13,6 +14,7 @@
    {
    	.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
    	.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
    	.pl1_min_power = 10000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 57000,
diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h
index 290a3a3..d02eaa1 100644
--- a/src/soc/intel/common/block/include/intelblocks/power_limit.h
+++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h
@@ -45,6 +45,7 @@
 struct cpu_tdp_power_limits {
    uint16_t mch_id;
    uint8_t cpu_tdp;
+	uint32_t power_limits_index;
    unsigned int pl1_min_power;
    unsigned int pl1_max_power;
    unsigned int pl2_min_power;
diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c
index 40a0857..b5fbe89 100644
--- a/src/soc/intel/common/block/power_limit/power_limit.c
+++ b/src/soc/intel/common/block/power_limit/power_limit.c
@@ -268,7 +268,8 @@
    	} else {
    		struct dptf_power_limits *settings = &config->controls.power_limits;
    		config_t *conf = config_of_soc();
-			struct soc_power_limits_config *soc_config = conf->power_limits_config;
+			struct soc_power_limits_config *soc_config =
+				&conf->power_limits_config[limits[index].power_limits_index];
    		settings->pl1.min_power = limits[index].pl1_min_power;
    		settings->pl1.max_power = limits[index].pl1_max_power;
    		settings->pl2.min_power = limits[index].pl2_min_power;