the following patch was just integrated into master: commit a2d4062d427d18127707306dada5e79d69bd3691 Author: Naresh G Solanki naresh.solanki@intel.com Date: Tue Aug 30 20:47:13 2016 +0530
soc/intel/skylake: Add FSP 2.0 support in ramstage
Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens.
Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Signed-off-by: Naresh G Solanki naresh.solanki@intel.com Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie dlaurie@chromium.org
See https://review.coreboot.org/16592 for details.
-gerrit