Change in coreboot[master]: crota: enable boot from SSD/ eMMC

[Scott Chao (Code Review)]

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63683 )

Change subject: crota: enable boot from SSD/ eMMC
......................................................................

crota: enable boot from SSD/ eMMC

- Fix eMMC reset/ enable GPIO pins.
- Fix clk_req and clk_src

BUG=b:229437061
BRANCH=none
TEST=build and without error

Signed-off-by: Scott Chao 
Change-Id: Id16e292ec7557d1780516a267bd752014d98e463
---
M src/mainboard/google/brya/variants/crota/overridetree.cb
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/63683/1

diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb
index 7a6b99e..1360bde 100644
--- a/src/mainboard/google/brya/variants/crota/overridetree.cb
+++ b/src/mainboard/google/brya/variants/crota/overridetree.cb
@@ -84,8 +84,8 @@
    	end
    	device ref pcie_rp3 on
    		chip soc/intel/common/block/pcie/rtd3
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
    			register "srcclk_pin" = "1"
    			device generic 0 alias emmc_rtd3 on end
    		end
@@ -120,10 +120,10 @@
    		end
    	end	#PCIE8 SD card
    	device ref pcie4_0 on
-			# Enable CPU PCIE RP 1 using CLK 1
+			# Enable CPU PCIE RP 1 using CLK 0
    		register "cpu_pcie_rp[CPU_RP(1)]" = "{
-				.clk_req = 1,
-				.clk_src = 1,
+				.clk_req = 0,
+				.clk_src = 0,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end