Change in coreboot[master]: gooble/kahlee: Use devicetree register values for UMA

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21335

Change subject: gooble/kahlee: Use devicetree register values for UMA
......................................................................

gooble/kahlee: Use devicetree register values for UMA

Modify Kahlee's OemPostParams() to vary the UMA settings passed to
AmdInitPost().

BUG=b:64927639
TEST=default, and 64, 128, 256, 384MB non-legacy configurations.

Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52
Signed-off-by: Marshall Dawson 
---
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/devicetree.cb
2 files changed, 28 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/21335/1

diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 2b3ac29..5da260b 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,8 +13,11 @@
  * GNU General Public License for more details.
  */

+#include <device/device.h>
 #include <agesawrapper.h>
 #include <PlatformMemoryConfiguration.h>
+#include <chip.h>
+#include <soc/pci_devs.h>

#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE

@@ -34,6 +37,27 @@

void OemPostParams(AMD_POST_PARAMS *PostParams)
 {
+	const struct soc_amd_stoneyridge_config *cfg;
+	const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+
+	if (!dev || !dev->chip_info)
+		printk(BIOS_ERR, "BUG! Could not find SoC devicetree config\n");
+	cfg = dev->chip_info;
+
    PostParams->MemConfig.PlatformMemoryConfiguration =
    			(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
+
+	if (IS_ENABLED(CONFIG_GFXUMA)) {
+		PostParams->MemConfig.UmaMode = cfg->uma_mode;
+		PostParams->MemConfig.UmaVersion = cfg->uma_type;
+		if (cfg->uma_mode == UMAMODE_SPECIFIED)
+			PostParams->MemConfig.UmaSize = cfg->uma_size;
+		else
+			PostParams->MemConfig.UmaSize = 0;
+	} else {
+		if (cfg->uma_mode != UMAMODE_NONE)
+			printk(BIOS_WARNING, "Warning: UMA mode was requested "
+					"but CONFIG_GFXUMA is not enabled\n");
+		PostParams->MemConfig.UmaMode = UMAMODE_NONE;
+	}
 }
diff --git a/src/mainboard/google/kahlee/devicetree.cb b/src/mainboard/google/kahlee/devicetree.cb
index 0ed3336..0be629b 100644
--- a/src/mainboard/google/kahlee/devicetree.cb
+++ b/src/mainboard/google/kahlee/devicetree.cb
@@ -18,6 +18,9 @@
    {
    	{ {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
    }"
+	register "uma_type" = "UMATYPE_LEGACY"
+	register "uma_mode" = "UMAMODE_AUTO"
+	register "uma_size" = "0"

device cpu_cluster 0 on
    	device lapic 10 on end