Attention is currently required from: Martin L Roth, Julius Werner.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68545 )
Change subject: console: Add a 32-bit vendor post-code call ......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68545/comment/edddce1c_f504c672 PS1, Line 7: vendor
I agree, I think this should be `soc_post_code()` since it seems to be meant to be implemented by co […]
Sounds good. Will update.
File src/console/post.c:
https://review.coreboot.org/c/coreboot/+/68545/comment/e4891f71_296ae110 PS1, Line 22: uint32_t
Looks like AMD systems use 32-bit "POST codes". […]
Yes, AMD is using 32-bit post codes. AMD CRBs use 32-bit values, and even the Google EC has been updated to be able to display 32-bit postcodes.
We want to have the standard post-codes be sent to the soc_post_code() routine, so that's why this is the way that it is. We're also going to have full 32-bit postcodes sent to soc_post_code. One of those patches comes immediately after this, and more are coming.
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Martin Roth (Code Review)