[XS] Change in coreboot[main]: soc/mediatek/common: Correct src clk frq to 400 MHz for eMMMC clk of ...

[Mengqi Zhang (Code Review)]

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Paul Menzel, Yidi Lin.

Mengqi Zhang has uploaded a new patch set (#15) to the change originally created by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )

Change subject: soc/mediatek/common: Correct src clk frq to 400 MHz for eMMMC clk of 400 kHz
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soc/mediatek/common: Correct src clk frq to 400 MHz for eMMMC clk
of 400 kHz

Mediatek SoCs start operating at eMMC clock around 3MHz right after
power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs
under 400kHz.

When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and get the
division value 128. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/128=3.125MHz.

So we correct source clock frequency to 400MHz for eMMC output
clock of 400KHz.

BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok

Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang 
Signed-off-by: Kiwi Liu 
---
M src/soc/mediatek/common/msdc.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/15