Change in coreboot[master]: soc/mediatek/mt8186: adjust usage of SRAM L2C

[Rex-BC Chen (Code Review)]

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60316 )

Change subject: soc/mediatek/mt8186: adjust usage of SRAM L2C
......................................................................

soc/mediatek/mt8186: adjust usage of SRAM L2C

The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
has configured only half of L2/L3 cache as SRAM. Therefore, decrease
the size of each SRAM region to fit into the first half of the cache.

BUG=b:207725851
TEST=Bootblock log looked good in `cbmem -c`

Signed-off-by: Rex-BC Chen 
Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
---
M src/soc/mediatek/mt8186/include/soc/memlayout.ld
1 file changed, 10 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60316/1

diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
index a1700e6..a409feb 100644
--- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
@@ -34,6 +34,11 @@
    /* MT8186 has 64KB SRAM. */
    SRAM_END(0x00110000)

+	/*
+	 * The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
+	 * has configured only half of L2/L3 cache as SRAM so we can't use them
+	 * unless if we disable L2C and reconfigure.
+	 */
    SRAM_L2C_START(0x00200000)
    /* 4K reserved for BOOTROM until BOOTBLOCK is started */
    BOOTBLOCK(0x00201000, 60K)
@@ -41,11 +46,11 @@
     * The needed size can be obtained by:
     *  aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
     */
-	DRAM_INIT_CODE(0x00210000, 240K)
-	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K)
-	PRERAM_CBFS_CACHE(0x00290000, 48K)
-	PRERAM_CBMEM_CONSOLE(0x0029C000, 400K)
-	SRAM_L2C_END(0x00300000)
+	DRAM_INIT_CODE(0x00210000, 196K)
+	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00241000, 140K)
+	PRERAM_CBFS_CACHE(0x00264000, 48K)
+	PRERAM_CBMEM_CONSOLE(0x00270000, 64K)
+	SRAM_L2C_END(0x00280000)

DRAM_START(0x40000000)
    DRAM_DMA(0x40000000, 1M)