Change in coreboot[master]: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 - coreboot-gerrit

28 Jan 2022


      Attention is currently required from: Maulik V Vaghela, Meera Ravindranath.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61266 )
Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61266/comment/546ad109_920d3838 
PS2, Line 12: Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com
BUG=b:216533766
TEST=<add_your_test_description_here>
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Gerrit-Change-Number: 61266
Gerrit-PatchSet: 2
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