Attention is currently required from: Jérémy Compostella, Paul Menzel, Shuo Liu.
yuchi.chen@intel.com has posted comments on this change by yuchi.chen@intel.com. ( https://review.coreboot.org/c/coreboot/+/83192?usp=email )
Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC ......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/6e3402be_3482d4e2?usp... : PS4, Line 100: This structure holds the DLL configuration : register values that will be programmed by RC. : Those policies should be used by platform if default values : provided by RC are not sufficient to provide stable operation : at all supported speed modes. RC will blindly set the DLL values : as provided in this structure.
Line breaks make it harder to read.
The FSP headers are not own by my team, I'm asking my colleagues for help now, please wait for some time.