[M] Change in coreboot[master]: soc/common/smbus: Add support for reading spd data via smbus for DDR5

[Paul Menzel (Code Review)]

Attention is currently required from: Angel Pons, Balaji Manigandan, Kapil Porwal, Karthik Ramasubramanian, Maulik Vaghela, Meera Ravindranath, Nick Vaccaro, Patrick Rudolph, Raj Astekar, Reka Norman, Subrata Banik, Subrata Banik, Tarun Tuli.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52731?usp=email )

Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5
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Patch Set 13:

(1 comment)

File src/soc/intel/common/block/smbus/smbuslib.c:

https://review.coreboot.org/c/coreboot/+/52731/comment/487c250a_6ca3fb6c :
PS13, Line 54: /*
             : 	*  By default,an SPD5 hub accepts 1 byte addressing pointing
             : 	*  to the first 128 bytes of memory. MR11[2:0] selects the page
             : 	*  pointer to address the entire 1024 bytes of non-volatile memory.
             : 	*/
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