Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51805 )
Change subject: soc/intel/xeon_sp: Prepare for CBnT BPM generation ......................................................................
soc/intel/xeon_sp: Prepare for CBnT BPM generation
To generate a working BPM, boot policy manifest for Intel CBnT the tool that generates it, requires ACPI base and PCH PWRM base as input. Therefore make it a Kconfig symbol, that can be used in Makefile.inc.
Change-Id: I6f1f9b53e34114682bd3258753f2d5aada9a530d Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/51805 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Christian Walter christian.walter@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 14 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Christian Walter: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 44028be..61ab750 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -82,6 +82,18 @@ int default 80
+config INTEL_ACPI_BASE_ADDRESS + hex + default 0x500 + help + IO Address of ACPI. + +config INTEL_PCH_PWRM_BASE_ADDRESS + hex + default 0xfe000000 + help + PCH PWRM Base address. + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 2df5f8b..ceaf271 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -19,7 +19,7 @@ #define SPI_BASE_SIZE 0x1000
#define TCO_BASE_ADDRESS 0x400 -#define ACPI_BASE_ADDRESS 0x500 +#define ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS #define ACPI_BASE_SIZE 0x100
/* Video RAM */ @@ -31,7 +31,7 @@
#define HECI1_BASE_ADDRESS 0xfed1a000
-#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS #define PCH_PWRM_BASE_SIZE 0x10000
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS