Patch set updated for coreboot: 2faf09c NOTFORMERGE: VX900 early init, and EPIA M850 board
Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1228
-gerrit
commit 2faf09ccb7fef47db12d17b5524fa79e02258837 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Tue May 21 14:51:26 2013 -0500
NOTFORMERGE: VX900 early init, and EPIA M850 board
I will split this up into pallatable chunks once the dependencies are merged.
This is the patch where all VX900 development is taking place. The NOTFORMERGE modifier is here to indicate that the code ain't ready.
=========================================================================== == Early initialization for VIA VX900: --------------------------------------------------------------------------- MMCONF: Works from very early ramstage. I am curently keeping MMCONF disabled during development. Enabling MMCONF only seems to save a few miliseconds of boot time. The plan is to change the MMCONF implementation in coreboot to allow dynamically changing the MMCONF_BASE, and then use the resource allocator to get a 256MB chunk for MMCONF. SMBUS is functional. RAMINIT: Raminit works with 1 rank, but not with several ranks. DRAM calibration when more than one DIMM is does not work well. Correct MRS command mapping not implemented for DIMMS which swap address pins. The delay calibration strategy is to put some predefined delays for the DQ input delays, and run hardware calibration on the other three delays (DQS input, DQ/DQS output). For the future, we could change this strategy to one that uses the hardware calibration of DQ input. Unfortunately, according to my testing, the DQ input delay calibration does not work reliably. Memtest runs through the serial console. It whines about memory errors during the random test (#7), but this seems to be because it tries to use the VGA memory hole (Errors start consistently at 128MB + 768K).
=========================================================================== == VX900 in ramstage: --------------------------------------------------------------------------- MP tables and IOAPIC: VX900 code enables the IOAPICs are enabled as long as they're declared in devicetree.cb. Since we rely on automatic MP table generation, if an IOAPIC is not properly declared, the code spits out an error, and continues without initializing it. LPC: Implemented LPC driver with basic interrupt routing. VGA: Still displays garbage and/or nothing. Video BIOS depends on proprietary interrupt handlers, some of which are implemented as YABEL interrupt handlers. If run in YABEL mode, the VGA BIOS requires access to other PCI devices and direct hardware access, it seems. GRUB2 and Linux are capable of initializing the VGA post-coreboot. Linux can use the VGA normally, but hangs after a while. SATA: The controller does not support AHCI, or a compliant SATA implementation. Normally SATA is done by setting RAID mode, but then SeaBIOS will not use it to boot. The only viable option is to keep the controller in native IDE mode. SATA device detection works reliably when one drive is attached. ATA DMA mode works reliably.
=========================================================================== == VIA EPIA M850 board: --------------------------------------------------------------------------- Minimal infrastructure to compile a coreboot image for this board is added. PIRQ_TABLE: Implemented, Linux can find and use irqs with "noapic acpi=off" MP_TABLE: Partially generated from devicetree.cb. Not tested.
KEYBOARD WORKS!!!
Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/include/lib.h | 1 + src/lib/ramtest.c | 35 + src/mainboard/via/Kconfig | 3 + src/mainboard/via/epia-m850/Kconfig | 50 + src/mainboard/via/epia-m850/Makefile.inc | 21 + src/mainboard/via/epia-m850/devicetree.cb | 111 ++ src/mainboard/via/epia-m850/irq_tables.c | 75 ++ src/mainboard/via/epia-m850/mainboard.c | 24 + src/mainboard/via/epia-m850/romstage.c | 131 +++ src/northbridge/via/Kconfig | 1 + src/northbridge/via/Makefile.inc | 1 + src/northbridge/via/vx900/Kconfig | 40 + src/northbridge/via/vx900/Makefile.inc | 42 + src/northbridge/via/vx900/chip.h | 52 + src/northbridge/via/vx900/chrome9hd.c | 391 +++++++ src/northbridge/via/vx900/ddr3_mrs_util.c | 214 ++++ src/northbridge/via/vx900/ddr3_mrs_util.h | 113 ++ src/northbridge/via/vx900/early_host_bus_ctl.c | 73 ++ src/northbridge/via/vx900/early_smbus.c | 209 ++++ src/northbridge/via/vx900/early_vx900.c | 133 +++ src/northbridge/via/vx900/early_vx900.h | 106 ++ src/northbridge/via/vx900/lpc.c | 220 ++++ src/northbridge/via/vx900/northbridge.c | 177 +++ src/northbridge/via/vx900/pcie.c | 142 +++ src/northbridge/via/vx900/raminit.h | 100 ++ src/northbridge/via/vx900/raminit_ddr3.c | 1440 ++++++++++++++++++++++++ src/northbridge/via/vx900/romstrap.inc | 60 + src/northbridge/via/vx900/romstrap.lds | 27 + src/northbridge/via/vx900/sata.c | 295 +++++ src/northbridge/via/vx900/traf_ctrl.c | 155 +++ src/northbridge/via/vx900/vx900.h | 78 ++ 31 files changed, 4520 insertions(+)
diff --git a/src/include/lib.h b/src/include/lib.h index 1f71d35..2f27149 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -37,6 +37,7 @@ void move_gdt(void); /* Defined in src/lib/ramtest.c */ void ram_check(unsigned long start, unsigned long stop); int ram_check_nodie(unsigned long start, unsigned long stop); +int ram_check_noprint_nodie(unsigned long start, unsigned long stop); void quick_ram_check(void);
/* Defined in src/lib/stack.c */ diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 3457210..192d573 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -223,6 +223,41 @@ int ram_check_nodie(unsigned long start, unsigned long stop) return ret; }
+int ram_check_noprint_nodie(unsigned long start, unsigned long stop) +{ + unsigned long addr, value, value2; + unsigned short int idx; + unsigned char failed, failures; + uint8_t verbose = 0; + + for (idx=0; idx<0x400; idx+=4) { + test_pattern(idx, &addr, &value); + write_phys(start + addr, value); + } + + /* Make sure we don't read before we wrote */ + phys_memory_barrier(); + + failures = 0; + for (idx=0; idx<0x400; idx+=4) { + test_pattern(idx, &addr, &value); + value2 = read_phys(start + addr); + + failed = (value2 != value); + failures |= failed; + if (failed && !verbose) { + } + if (verbose) { + } + } + if (failures) { + return 1; + } + else { + } + return 0; +} + void quick_ram_check(void) { int fail = 0; diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig index 6980548..48f4055 100644 --- a/src/mainboard/via/Kconfig +++ b/src/mainboard/via/Kconfig @@ -9,6 +9,8 @@ config BOARD_VIA_EPIA_CN bool "EPIA-CN" config BOARD_VIA_EPIA_M700 bool "EPIA-M700" +config BOARD_VIA_EPIA_M850 + bool "EPIA-M850" config BOARD_VIA_EPIA_M bool "EPIA-M" config BOARD_VIA_EPIA_N @@ -23,6 +25,7 @@ endchoice source "src/mainboard/via/epia/Kconfig" source "src/mainboard/via/epia-cn/Kconfig" source "src/mainboard/via/epia-m700/Kconfig" +source "src/mainboard/via/epia-m850/Kconfig" source "src/mainboard/via/epia-m/Kconfig" source "src/mainboard/via/epia-n/Kconfig" source "src/mainboard/via/pc2500e/Kconfig" diff --git a/src/mainboard/via/epia-m850/Kconfig b/src/mainboard/via/epia-m850/Kconfig new file mode 100644 index 0000000..6c840a6 --- /dev/null +++ b/src/mainboard/via/epia-m850/Kconfig @@ -0,0 +1,50 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011-2012 Alexandru Gagniuc mr.nuke.me@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see http://www.gnu.org/licenses/. +## + +if BOARD_VIA_EPIA_M850 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_VIA_NANO + select NORTHBRIDGE_VIA_VX900 + select SUPERIO_FINTEK_F81865F + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select HAVE_MP_TABLE + #select HAVE_OPTION_TABLE + #select HAVE_ACPI_TABLES + #select HAVE_ACPI_RESUME + #select BOARD_HAS_FADT + select BOARD_ROMSIZE_KB_512 + select DRIVERS_GENERIC_IOAPIC + +config MAINBOARD_DIR + string + default via/epia-m850 + +config MAINBOARD_PART_NUMBER + string + default "EPIA-M850" + +config IRQ_SLOT_COUNT + int + default 13 + +endif # BOARD_VIA_EPIA_M850 diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc new file mode 100644 index 0000000..9c6d31f --- /dev/null +++ b/src/mainboard/via/epia-m850/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc mr.nuke.me@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see http://www.gnu.org/licenses/. +## + +#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c + diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb new file mode 100644 index 0000000..3ee56b4 --- /dev/null +++ b/src/mainboard/via/epia-m850/devicetree.cb @@ -0,0 +1,111 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc mr.nuke.me@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see http://www.gnu.org/licenses/. +## + +chip northbridge/via/vx900 # Northbridge + register "assign_pex_to_dp" = "0" + register "pcie_port1_2_lane_wide" = "1" + register "ext_int_route_to_pirq" = "'H'" + + device cpu_cluster 0 on # APIC cluster + chip cpu/via/nano # VIA NANO + device lapic 0 on end # APIC + end + end + device domain 0 on + device pci 0.0 on end # [0410] Host controller + device pci 0.1 on end # [1410] Error Reporting + device pci 0.2 on end # [2410] CPU Bus Control + device pci 0.3 on end # [3410] DRAM Bus Control + device pci 0.4 on end # [4410] Power Management + device pci 0.5 on # [5410] APIC+Traffic Control + chip drivers/generic/ioapic + register "have_isa_interrupts" = "0" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfecc0000" + device ioapic 2 on end + end + end + device pci 0.6 off end # [6410] Scratch Registers + device pci 0.7 on end # [7410] V4 Link Control + device pci 1.0 on # [7122] VGA Chrome9 HD + ioapic_irq 2 INTA 0x28 + end + device pci 1.1 on # [9170] Audio Device + ioapic_irq 2 INTA 0x29 + end + device pci 3.0 on end # [a410] PEX1 + device pci 3.1 on end # [b410] PEX2 + device pci 3.2 on end # [c410] PEX3 + device pci 3.3 on end # [d410] PEX4 + device pci 3.4 on end # [e410] PCIE bridge + device pci b.0 on end # [a409] USB Device + device pci c.0 off end # [95d0] SDIO Host Controller + device pci d.0 off end # [9530] Memory Card controller + device pci f.0 on # [9001] SATA Controller + ioapic_irq 1 INTA 0x15 + end + device pci 10.0 on end # [3038] USB 1.1 + device pci 10.1 on end # [3038] USB 1.1 + device pci 10.2 on end # [3038] USB 1.1 + device pci 10.3 on end # [3038] USB 1.1 + device pci 10.4 on end # [3104] USB 2.0 + device pci 11.0 on # [8410] LPC Bus Control + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfec00000" + device ioapic 1 on end + end + #chip drivers/generic/generic # DIMM 0 channel 1 + # device i2c 50 on end + #end + #chip drivers/generic/generic # DIMM 1 channel 1 + # device i2c 51 on end + #end + chip superio/fintek/f81865f # Super duper IO + device pnp 4e.0 off end # Floppy + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 off end # Keyboard not here + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 10 + end + device pnp 4e.13 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 11 + end + end # superio/fintek/f81865f + end # LPC + device pci 11.7 on end # [a353] North-South control + device pci 14.0 on end # [3288] Azalia HDAC + end +end diff --git a/src/mainboard/via/epia-m850/irq_tables.c b/src/mainboard/via/epia-m850/irq_tables.c new file mode 100644 index 0000000..28fbb4f --- /dev/null +++ b/src/mainboard/via/epia-m850/irq_tables.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <string.h> /* <- For memset */ + +#define _OFF 0x00 +#define ___OFF 0x0000 +#define LNKA 1 +#define LNKB 2 +#define LNKC 3 +#define LNKD 4 +#define LNKE 5 +#define LNKF 6 +#define LNKG 7 +#define LNKH 8 +#define BITMAP 0xdce0 +/* The link that carries the SATA interrupt has its own mask, just in case + * we want to make sure our SATA controller gets mapped to IRQ 14 */ +#define B_SATA BITMAP + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 13, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x11 << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively for PCI */ + PCI_VENDOR_ID_VIA, /* Vendor */ + PCI_DEVICE_ID_VIA_VX900_LPC, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x19, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0}, + {0x00, (0x0b << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x0c << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x0d << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x0f << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0}, + {0x00, (0x14 << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x1, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x2, 0x0}, + {0x03, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, + {0x04, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c new file mode 100644 index 0000000..57b12e1 --- /dev/null +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <device/device.h> + +struct chip_operations mainboard_ops = { + CHIP_NAME("VIA EPIA-M850 Mainboard") +}; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c new file mode 100644 index 0000000..03a8520 --- /dev/null +++ b/src/mainboard/via/epia-m850/romstage.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* + * Inspired from the EPIA-M700 + */ +#undef CONFIG_COLLECT_TIMESTAMPS +#define CONFIG_COLLECT_TIMESTAMPS 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <console/console.h> +#include <lib.h> +#include <cpu/x86/bist.h> +#include <string.h> +#include <timestamp.h> + +#include <console/cbmem_console.h> + +#include "northbridge/via/vx900/early_vx900.h" +#include "northbridge/via/vx900/raminit.h" +#include "superio/fintek/f81865f/f81865f_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x4e, 0x10) + +static inline u64 tsc2u64(tsc_t tsc) +{ + return ((u64)tsc.hi << 32) | tsc.lo; +} +#define TSC_PER_USEC 1297 +static inline u32 tsc2ms(u64 end, u64 start) +{ + return ((u32)(end-start)/TSC_PER_USEC)/1000; +} +/* cache_as_ram.inc jumps to here. */ +void main(unsigned long bist); +void main(unsigned long bist) +{ + tsc_t tsc_at_romstage_start = rdtsc();; + + /* First thing we need to do on the VX900, before anything else */ + vx900_enable_pci_config_space(); + + f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + print_debug("Console initialized. \n"); + + vx900_cpu_bus_interface_setup(); + + /* Keyboard off */ + //pci_mod_config8(LPC, 0x51, (1<<2)|(1<<0), 0); + /* NOT HERE FIXME */ + pci_write_config8(SNMIC, 0x60, 1 << (30-24)); + + /* Be smart. Get this info */ + vx900_print_strapping_info(); + /* DEVEL helper */ + vx900_disable_auto_reboot(); + /* Halt if there was a built-in self test failure. */ + report_bist_failure(bist); + + /* Oh, almighty, give us the SMBUS */ + enable_smbus(); + + /* If this works, then SMBUS is up and running */ + /* dump_spd_data(); */ + + tsc_t tsc_before_raminit = rdtsc(); + /* Now we can worry about raminit. + * This board only has DDR3, so no need to worry about which DRAM type + * to use */ + dimm_layout dimms = {{0x50, 0x51, SPD_END_LIST}}; + vx900_init_dram_ddr3(&dimms); + tsc_t tsc_after_raminit = rdtsc(); + + ram_check(0, 0x80); + ram_check(512<<10, 0x80); + ram_check(1024<<10, 0x80); + ram_check((1<<20) - (1<<10), 0x80); + ram_check((1<<24), 0x80); + ram_check((512 + 256 -1)<<20, 0x80); + ram_check(0x80c0000, 0x80); + + print_debug("We passed RAM verify\n"); +#ifdef GONFIG_EARLY_CBMEM_INIT + /* We got RAM working, now we can write the timestamps to RAM */ + cbmem_initialize(); + timestamp_init(tsc_at_romstage_start); + timestamp_add(TS_START_ROMSTAGE, tsc_at_romstage_start ); + timestamp_add(TS_BEFORE_INITRAM, tsc_before_raminit ); + timestamp_add(TS_AFTER_INITRAM, tsc_after_raminit ); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + /* FIXME: Take this out please */ + /* This disables our USB */ + //pci_write_config8(LPC, 0x50, ~(1<<3)); + /* This eviscerates our VGA out of existence */ + //pci_mod_config16(MCU, 0xa0, (1 << 15), 0); + /* Disable Memcard and SDIO */ + pci_mod_config8(LPC, 0x51, 0, (1<<7) | (1<<4)); + + /* FIXME: They no es belong here */ + u64 start, end; + start = tsc2u64(tsc_at_romstage_start); + end = tsc2u64(tsc_before_raminit); + printk(BIOS_DEBUG, "Before raminit %ums\n", tsc2ms(end, start)); + + start = end; + end = tsc2u64(tsc_after_raminit); + printk(BIOS_DEBUG, "Actual Raminit %ums\n", tsc2ms(end, start)); +} diff --git a/src/northbridge/via/Kconfig b/src/northbridge/via/Kconfig index 2c38acf..8a747b9 100644 --- a/src/northbridge/via/Kconfig +++ b/src/northbridge/via/Kconfig @@ -4,3 +4,4 @@ source src/northbridge/via/cn400/Kconfig source src/northbridge/via/vt8601/Kconfig source src/northbridge/via/vt8623/Kconfig source src/northbridge/via/vx800/Kconfig +source src/northbridge/via/vx900/Kconfig diff --git a/src/northbridge/via/Makefile.inc b/src/northbridge/via/Makefile.inc index 75cb15b..2e74b61 100644 --- a/src/northbridge/via/Makefile.inc +++ b/src/northbridge/via/Makefile.inc @@ -4,4 +4,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700 subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700 subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN400) += cn400 subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX800) += vx800 +subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX900) += vx900
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig new file mode 100644 index 0000000..d8dc05a --- /dev/null +++ b/src/northbridge/via/vx900/Kconfig @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc mr.nuke.me@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see http://www.gnu.org/licenses/. +## + +config NORTHBRIDGE_VIA_VX900 + bool + select IOAPIC + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + select HAVE_HARD_RESET + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select GFXUMA + +config MAX_PIRQ_LINKS + int + default 8 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config VGA_BIOS_ID + string + default "1106,7122" \ No newline at end of file diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc new file mode 100644 index 0000000..23bbcdc --- /dev/null +++ b/src/northbridge/via/vx900/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011-2013 Alexandru Gagniuc mr.nuke.me@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see http://www.gnu.org/licenses/. +## + +romstage-y += early_smbus.c +romstage-y += early_vx900.c +romstage-y += early_host_bus_ctl.c +romstage-y += raminit_ddr3.c +romstage-y += ./../../../device/dram/ddr3.c +romstage-y += ./../../../southbridge/via/common/early_smbus.c +romstage-y += ./../../../drivers/pc80/udelay_io.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += ./../../../lib/cbmem.c + +ramstage-y += pcie.c +ramstage-y += northbridge.c +ramstage-y += chrome9hd.c +ramstage-y += traf_ctrl.c +ramstage-y += sata.c +ramstage-y += lpc.c + +# The buildsystem only includes this file if CONFIG_VGA is selected. +# We need to do some VGA I/O before the VGA can be initialized. We can make good +# use of some of the functions there, so include them unconditionally +ramstage-y += ./../../../drivers/pc80/vga/vga_io.c + +chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc +chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h new file mode 100644 index 0000000..6334a8e --- /dev/null +++ b/src/northbridge/via/vx900/chip.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +struct northbridge_via_vx900_config { + /** + * \brief PCIe Lane[3:0] Function Select + * + * PCIe Lane3~Lane0 (PEXTX[3:0]P/VCC) can be used by the integrated + * graphic controller to output its display data. The PCIe lanes will + * be used to output DisplayPort data. + */ + u8 assign_pex_to_dp; + + /** + * \brief Lane Width for Root Port 1 + * + * Two PCIe lanes are used for Root port 1. Root port 2 is disabled. + */ + u8 pcie_port1_2_lane_wide; + + /** + * \brief PIRQ line to which to route the external interrupt + * + * The VX900 features an external interrupt which can be routed to any + * of the PIRQA->PIRQH lines. Usually, on-board devices are connected + * to the external interrupt. In some vendor BIOS's pirq table, this + * appears as link 9. + * + * Setting this line only affects the behavior of the integrated PIC. It + * has no effect on the IOAPIC. + * + * The value of this register must be a literal upper-case character + * from 'A' to 'H'. + */ + char ext_int_route_to_pirq; +}; diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c new file mode 100644 index 0000000..1f3ed99 --- /dev/null +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -0,0 +1,391 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <arch/io.h> +#include <config.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/vga_io.h> + +#include "vx900.h" + +#define CHROME_9_HD_MIN_FB_SIZE 8 +#define CHROME_9_HD_MAX_FB_SIZE 512 + +/* Helper to determine the framebuffer size */ +u32 chrome9hd_fb_size(void) +{ + static u32 fb_size = 0; + u32 size_mb; + /* We do some PCI and CMOS IO to find our value, so if we've already + * found it, save some time */ + if (fb_size != 0) + return fb_size; + /* FIXME: read fb_size from CMOS, but until that is implemented, start + * from 512MB */ + size_mb = 512; + + /* The minimum framebuffer size is 8MB. */ + size_mb = max(size_mb, CHROME_9_HD_MIN_FB_SIZE); + + const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, + 0); + /* + * We have two limitations on the maximum framebuffer size: + * 1) (Sanity) No more that 1/4 of system RAM + * 2) (Hardware limitation) No larger than DRAM in last rank + * Check both of these limitations and apply them to our framebuffer */ + u32 tomm = (pci_read_config16(mcu, 0x88) & 0x07ff) << (24 - 20); + u32 max_sizem = tomm >> 2; + if (size_mb > max_sizem) { + printk(BIOS_ALERT, "The framebuffer size of of %dMB is larger" + " than 1/4 of available memory.\n" + " Limiting framebuffer to %dMB\n", size_mb, max_sizem); + size_mb = max_sizem; + } + + /* Now handle limitation #2 + * Look at the ending address of the memory ranks, from last to first, + * until we find one that is not zero. That is our last rank, and its + * size is the limit of our framebuffer. */ + int i; + for (i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) { + u8 reg8 = pci_read_config8(mcu, 0x40 + 1); + if (reg8 == 0) + continue; + /* We've reached the last populated rank */ + u8 ranksize = reg8 - pci_read_config8(mcu, 0x48 + i); + max_sizem = ranksize >> 6; + }; + if (size_mb > max_sizem) { + printk(BIOS_ALERT, "The framebuffer size of of %dMB is larger" + " than size of the last DRAM rank.\n" + " Limiting framebuffer to %dMB\n", size_mb, max_sizem); + size_mb = max_sizem; + } + + /* Now round the framebuffer size to the closest power of 2 */ + u8 fb_pow = 0; + while (size_mb >> fb_pow) + fb_pow++; + fb_pow--; + size_mb = (1 << fb_pow); + /* We store the framebuffer size in bytes, for simplicity */ + fb_size = size_mb << 20; + return fb_size; +} + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +static int vx900_int15_handler_yabel(void) +{ + printk(BIOS_DEBUG, "%s %0x\n", __func__, M.x86.R_AX & 0xffff); + /* Set AX return value here so we don't set it every time. Just set it + * to something else if the callback is unsupported */ + int res = -1; + switch (M.x86.R_AX & 0xffff) { +#if 0 + case 0x5f01: + /* VGA POST - panel type */ + /* FIXME: Don't hardcode panel type */ + M.x86.R_CX = 2; /* Panel Type Number */ + break; + case 0x5f02: + { + /* Boot device selection */ + u8 hw_opt = 1 << 0; /* DVI not, CRT present */ + u8 hdtv_conf2 = 1 << 2; /* Connector type: R/G/B */ + u8 tv_conf2 = 1 << 2; /* Only RGB */ + M.x86.R_EBX = + (hdtv_conf2 << 16) | (tv_conf2 << 8) | hw_opt; + u16 dev_word = 0x2383; /* CRT1/2, LCD1/2, HDMI1/2 */ + u8 tv_conf1 = 0; /* Default RGB NTSC */ + u8 hdtv_conf1 = 0x06; /* 1080P HDTV */ + M.x86.R_ECX = + (hdtv_conf1 << 24) | (tv_conf1 << 16) | dev_word; + M.x86.R_DL = 9; /* Layout I, RGB */ + /* FIXME: zero just make VBIOS autosense */ + M.x86.R_EBX = 0; + M.x86.R_ECX = 0; + M.x86.R_DL = 0; + break; + } +#endif + case 0x5f18: + { + /* + * BL Bit[7:4] + * Memory Data Rate + * 0000: 66MHz + * 0001: 100MHz + * 0010: 133MHz + * 0011: 200MHz ( DDR200 ) + * 0100: 266MHz ( DDR266 ) + * 0101: 333MHz ( DDR333 ) + * 0110: 400MHz ( DDR400 ) + * 0111: 533MHz ( DDR I/II 533 + * 1000: 667MHz ( DDR I/II 667) + * Bit[3:0] + * N: Frame Buffer Size 2^N MB + */ + u8 i; + device_t dev; + dev = dev_find_slot(0, PCI_DEVFN(0, 3)); + i = pci_read_config8(dev, 0xa1); + printk(BIOS_DEBUG, "Got 0.3 0xa1: %.2x\n", i); + M.x86.R_BX = (u32) ((i & 0x70) >> 4) + 2; + printk(BIOS_DEBUG, "Wrote R_BX: %x\n", M.x86.R_BX); + i = pci_read_config8(dev, 0x90); + printk(BIOS_DEBUG, "Got 0.3 0x90: %.2x\n", i); + i = ((i & 0x07)) << 4; + M.x86.R_BX |= (u32) i; + printk(BIOS_DEBUG, "Wrote R_BX: %x\n", M.x86.R_BX); + break; + } +#if 0 + case 0x5f2a: + /* Get SSC Control Settings */ + /* FIXME: No idea what this does. Just disable this feature + * for now */ + M.x86.R_CX = 0; + break; + case 0x5f2b: + /* Engine clock setting */ + M.x86.R_EBX = 0x0000004; /* FIXME: ECLK fixed 250MHz ? */ + break; + default: + printk(BIOS_DEBUG, "Unsupported INT15 call %04x!\n", + M.x86.R_AX & 0xffff); + M.x86.R_AX = 0; + res = -1; + break; + #endif + } + + if (res == 0) + M.x86.R_AX = 0x5f; + else + M.x86.R_AX = 0; + return res; +} + +static void vx900_vga_set_int15_handler(void) +{ + printk(BIOS_DEBUG, "Our int15 handler is at %p\n", + &vx900_int15_handler_yabel); + typedef int (*yabel_handleIntFunc) (void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = vx900_int15_handler_yabel; +} +#else +static void vx900_vga_set_int15_handler(void) +{ +}; +#endif + +static void chrome9hd_set_sid_vid(u16 vendor, u16 device) +{ + vga_sr_write(0x36, vendor >> 8); /* SVID high byte */ + vga_sr_write(0x35, vendor & 0xff); /* SVID low byte */ + vga_sr_write(0x38, device >> 8); /* SID high byte */ + vga_sr_write(0x37, device & 0xff); /* SID low byte */ +} + +static void chrome9hd_handle_uma(device_t dev) +{ + /* Mirror mirror, shiny glass, tell me that is not my ass */ + u32 fb_size = chrome9hd_fb_size() >> 20; + + //uma_resource(dev, 0x18, uma_memory_base>>10, uma_memory_size>>10); + + printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, + uma_memory_base >> 20); + printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size, + uma_memory_size >> 20); + u8 fb_pow = 0; + while (fb_size >> fb_pow) + fb_pow++; + fb_pow--; + + /* Step 6 - Let MCU know the framebuffer size */ + device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + pci_mod_config8(mcu, 0xa1, 7 << 4, (fb_pow - 2) << 4); + + /* Step 7 - Let GFX know the framebuffer size (through PCI and IOCTL) + * The size we set here affects the behavior of BAR2, and the amount of + * MMIO space it requests. The default is 512MB, so if we don't set this + * before reading the resources, we could waste space below 4G */ + pci_write_config8(dev, 0xb2, ((0xff << (fb_pow - 2)) & ~(1 << 7))); + vga_sr_write(0x68, (0xff << (fb_pow - 1))); + /* And also that the framebuffer is in the system, RAM */ + pci_mod_config8(dev, 0xb0, 0, 1 << 0); +} + +static void chrome9hd_biosguide_init_seq(device_t dev) +{ + device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + device_t host = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0); + + /* Step 1 - Enable VGA controller */ + /* FIXME: This is the VGA hole @ 640k-768k, and the vga port io + * We need the port IO, but can we disable the memory hole? */ + pci_mod_config8(mcu, 0xa4, 0, 0x80); /* VGA memory hole */ + + /* Step 2 - Forward MDA cycles to GFX */ + pci_mod_config8(host, 0x4e, 1 << 1, 0); /* FIXME */ + + /* Step 3 - Enable GFX I/O space */ + pci_mod_config8(dev, PCI_COMMAND, 0, PCI_COMMAND_IO); + + /* Step 4 - Enable video subsystem */ + vga_enable_mask(1 << 0, 1 << 0); + + /* Step 5 - Unlock accessing of IO space */ + vga_sr_write(0x10, 0x01); + + chrome9hd_handle_uma(dev); + + /* Step 8 - Enable memory base register on the GFX */ + if (uma_memory_base == 0) + die("uma_memory_base not set. Abandon ship!\n"); + printk(BIOS_DEBUG, "UMA base 0x%.10llx (%lluMB)\n", uma_memory_base, + uma_memory_base >> 20); + vga_sr_write(0x6d, (uma_memory_base >> 21) & 0xff); /* base 28:21 */ + vga_sr_write(0x6e, (uma_memory_base >> 29) & 0xff); /* base 36:29 */ + vga_sr_write(0x6f, 0x00); /* base what what in the butt ?? */ + + /* Step 9 - Set SID/VID */ + chrome9hd_set_sid_vid(0x1106, 0x7122); + +} + +static void dump_pci_device(device_t dev) +{ + int i; + for (i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + if ((i & 7) == 0) + print_debug(" |"); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} + +static void chrome9hd_init(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD INIT\n"); + print_debug("======================================================\n"); + + chrome9hd_biosguide_init_seq(dev); + + /* Prime PLL FIXME: bad comment */ + vga_sr_mask(0x3c, 1 << 2, 1 << 2); + + //VGA IO Address Select. 3B5 or 3D5? + vga_misc_mask(1 << 0, 1 << 0); + + //enable Base VGA 16 Bits Decode + //pci_mod_config8(host, 0x4e, 0, 1<<4); + + vx900_vga_set_int15_handler(); + + u32 fb_address = pci_read_config32(dev, PCI_BASE_ADDRESS_2); + fb_address &= ~0x0F; + if (!fb_address) { + printk(BIOS_WARNING, "Chrome9HD: No FB BAR assigned!\n"); + return; + } + + printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n", + 256, fb_address); + +#if 0 + /* Poison the framebuffer */ + size_t i, j; + for(i = 0; i < 256; i++) { + u32 * fb = (u32*) (u32)(fb_address + i * (1<<20)); + for(j = 0; j < (1<<20)>>2; j++) { + fb[j] = 0xdeadbeef; + } + } +#endif + + printk(BIOS_DEBUG, "Initializing VGA...\n"); + + pci_dev_init(dev); + + printk(BIOS_DEBUG, "Enable VGA console\n"); + + dump_pci_device(dev); +} + +static void chrome9hd_enable(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD ENABLE\n"); + print_debug("======================================================\n"); + + device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + /* FIXME: here? -=- ACLK 250Mhz */ + pci_mod_config8(mcu, 0xbb, 0, 0x01); +} + +static void chrome9hd_disable(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD DISABLE\n"); + print_debug("======================================================\n"); + + device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + /* Disable GFX - This step effectively renders the GFX inert + * It won't even show up as a PCI device during enumeration */ + pci_mod_config8(mcu, 0xa1, 1 << 7, 0); +} + +static struct device_operations chrome9hd_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = chrome9hd_init, + .disable = chrome9hd_disable, + .enable = chrome9hd_enable, + .ops_pci = 0, +}; + +static const struct pci_driver chrome9hd_driver __pci_driver = { + .ops = &chrome9hd_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_VGA, +}; diff --git a/src/northbridge/via/vx900/ddr3_mrs_util.c b/src/northbridge/via/vx900/ddr3_mrs_util.c new file mode 100644 index 0000000..0ea2761 --- /dev/null +++ b/src/northbridge/via/vx900/ddr3_mrs_util.c @@ -0,0 +1,214 @@ +#include "ddr3_mrs_util.h" +//#include <../../dram/dram.h> + +/* + * MRS command structure: + * cmd[15:0] = Address pins MA[15:0] + * cmd[18:16] = Bank address BA[2:0] + */ + +static u8 ddr3_twr_to_mr0_map(u8 twr) +{ + if (twr >= 5 && twr <= 8) + return (twr - 4) << 9; + + if (twr >= 10 && twr <= 14) + return (twr >> 1) << 9; + + /* tWR == 16T is [000] */ + return 0; +} + + +/* Map the cas latency to a bitmask for the MR0 cycle */ +static u16 ddr3_cas_to_mr0_map(u8 cas) +{ + u16 mask = 0; + /* A[6:4] are bits [2:0] of (CAS - 4) */ + mask = ((cas - 4) & 0x07) << 4; + + /* A2 is the MSB of (CAS - 4) */ + if ((cas - 4) & (1 << 4)) + mask |= (1 << 2); + + return mask; +} + +mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, + u8 write_recovery, + enum ddr3_mr0_dll_reset dll_reset, + enum ddr3_mr0_mode mode, + u8 cas, + enum ddr3_mr0_burst_type burst_type, + enum ddr3_mr0_burst_length burst_lenght) +{ + mrs_cmd_t cmd = 0 << 16; + + if (precharge_pd == DDR3_MR0_PRECHARGE_FAST) + cmd |= (1 << 12); + + cmd |= ddr3_twr_to_mr0_map(write_recovery); + + if (dll_reset == DDR3_MR0_DLL_RESET_YES) + cmd |= (1 << 8); + + if (mode == DDR3_MR0_MODE_TEST) + cmd |= (1 << 7); + + cmd |= ddr3_cas_to_mr0_map(cas); + + if (burst_type == DDR3_MR0_BURST_TYPE_INTERLEAVED) + cmd |= (1 << 3); + + cmd |= (burst_lenght & 0x03) << 0; + + return cmd; +} + +static u16 ddr3_rtt_nom_to_mr1_map(enum ddr3_mr1_rtt_nom rtt_nom) +{ + u16 mask = 0; + /* A9 <-> rtt_nom[2] */ + if (rtt_nom & (1 << 2)) + mask |= (1 << 9); + /* A6 <-> rtt_nom[1] */ + if (rtt_nom & (1 << 1)) + mask |= (1 << 6); + /* A2 <-> rtt_nom[0] */ + if (rtt_nom & (1 << 0)) + mask |= (1 << 2); + + return mask; +} + +static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods) +{ + u16 mask = 0; + /* A5 <-> ods[1] */ + if (ods & (1 << 1)) + mask |= (1 << 5); + /* A1 <-> ods[0] */ + if (ods & (1 << 0)) + mask |= (1 << 1); + + return mask; +} + +mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, + enum ddr3_mr1_tqds tqds, + enum ddr3_mr1_rtt_nom rtt_nom, + enum ddr3_mr1_write_leveling write_leveling, + enum ddr3_mr1_ods ods, + enum ddr3_mr1_additive_latency additive_latency, + enum ddr3_mr1_dll dll_disable) +{ + mrs_cmd_t cmd = 1 << 16; + + if (qoff == DDR3_MR1_QOFF_DISABLE) + cmd |= (1 << 12); + + if (tqds == DDR3_MR1_TQDS_ENABLE) + cmd |= (1 << 11); + + cmd |= ddr3_rtt_nom_to_mr1_map(rtt_nom); + + if (write_leveling == DDR3_MR1_WRLVL_ENABLE) + cmd |= (1 << 7); + + cmd |= ddr3_ods_to_mr1_map(ods); + + cmd |= (additive_latency & 0x03) << 3; + + if (dll_disable == DDR3_MR1_DLL_DISABLE) + cmd |= (1 << 0); + + return cmd; +} + +mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, + enum ddr3_mr2_srt_range extended_temp, + enum ddr3_mr2_asr self_refresh, + u8 cas_cwl) +{ + mrs_cmd_t cmd = 2 << 16; + + cmd |= (rtt_wr & 0x03) << 9; + + if (extended_temp == DDR3_MR2_SRT_EXTENDED) + cmd |= (1 << 7); + + if (self_refresh == DDR3_MR2_ASR_AUTO) + cmd |= (1 << 6); + + cmd |= ((cas_cwl - 5) & 0x07) << 3; + + return cmd; +} + + +mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) +{ + mrs_cmd_t cmd = 3 << 16; + + if(dataflow_from_mpr) + cmd |= (1 << 2); + + return cmd; +} + +mrs_cmd_t ddr3_mrs_swap_pins(mrs_cmd_t cmd); + +/* Swap some bitties titties: + * + * MA3 <-> MA4 + * MA5 <-> MA6 + * MA7 <-> MA8 + * BA0 <-> BA1 + */ +mrs_cmd_t ddr3_mrs_swap_pins(mrs_cmd_t cmd) +{ + u32 downshift, upshift; + /* High bits= A4 | A6 | A8 | BA1 */ + /* Low bits = A3 | A5 | A7 | BA0 */ + u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16); + downshift = (cmd & (lowbits << 1)); + upshift = (cmd & lowbits); + cmd &= ~(lowbits | (lowbits << 1)); + cmd |= (downshift >> 1) | (upshift << 1); + return cmd; +} + +/* + * Translate the MRS command into the memory address corresponding to the + * command. This is based on the CPU address to memory address mapping described + * by the initial values of registers 0x52 and 0x53, so do not fuck with them + * until after the MRS commands have been sent to all ranks + */ + +u32 vx900_get_mrs_addr(mrs_cmd_t cmd); +/* + * Translate the MRS command into an address on the CPU bus + * + * Take an MRS command (mrs_cmd_t) and translate it to a read address on the CPU + * bus. Thus, reading from the returned address, will issue the correct MRS + * command. + * + * A read from the returned address will produce the correct MRS command + * provided the following conditions are met: + * - The MA pin mapping is set to VX900_MRS_MA_MAP + * - The memory controller's Fun3_RX6B[2:0] is set to 011b (MSR Enable) + */ +u32 vx900_get_mrs_addr(mrs_cmd_t cmd) +{ + u32 addr = 0; + u8 mrs_type = (cmd >> 16) & 0x07; + /* MA[9:0] <-> A[12:3] */ + addr |= ((cmd & 0x3ff) << 3); + /* MA10 <-> A20 */ + addr |= (((cmd >> 10) & 0x1) << 20); + /* MA[12:11] <-> A[14:13] */ + addr |= (((cmd >> 11) & 0x3) << 13); + /* BA[2:0] <-> A[19:17] */ + addr |= mrs_type << 17; + return addr; +} diff --git a/src/northbridge/via/vx900/ddr3_mrs_util.h b/src/northbridge/via/vx900/ddr3_mrs_util.h new file mode 100644 index 0000000..5d4bd88 --- /dev/null +++ b/src/northbridge/via/vx900/ddr3_mrs_util.h @@ -0,0 +1,113 @@ +#ifndef REDUNDANT_H +#define REDUNDANT_H + +#include <stdint.h> + +typedef u32 mrs_cmd_t; + +enum ddr3_mr0_precharge { + DDR3_MR0_PRECHARGE_SLOW = 0, + DDR3_MR0_PRECHARGE_FAST = 1, +}; +enum ddr3_mr0_mode { + DDR3_MR0_MODE_NORMAL = 0, + DDR3_MR0_MODE_TEST = 1, +}; +enum ddr3_mr0_dll_reset { + DDR3_MR0_DLL_RESET_NO = 0, + DDR3_MR0_DLL_RESET_YES = 1, +}; +enum ddr3_mr0_burst_type { + DDR3_MR0_BURST_TYPE_SEQUENTIAL = 0, + DDR3_MR0_BURST_TYPE_INTERLEAVED = 1, +}; +enum ddr3_mr0_burst_length { + DDR3_MR0_BURST_LENGTH_8 = 0, + DDR3_MR0_BURST_LENGTH_CHOP = 1, + DDR3_MR0_BURST_LENGTH_4 = 2, +}; +/** + * \brief Get command address for a DDR3 MR0 command + */ +mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, + u8 write_recovery, + enum ddr3_mr0_dll_reset dll_reset, + enum ddr3_mr0_mode mode, + u8 cas, + enum ddr3_mr0_burst_type interleaved_burst, + enum ddr3_mr0_burst_length burst_lenght +); + +enum ddr3_mr1_qoff { + DDR3_MR1_QOFF_ENABLE = 0, + DDR3_MR1_QOFF_DISABLE = 1, +}; +enum ddr3_mr1_tqds { + DDR3_MR1_TQDS_DISABLE = 0, + DDR3_MR1_TQDS_ENABLE = 1, +}; +enum ddr3_mr1_write_leveling { + DDR3_MR1_WRLVL_DISABLE = 0, + DDR3_MR1_WRLVL_ENABLE = 1, +}; +enum ddr3_mr1_rtt_nom { + DDR3_MR1_RTT_NOM_OFF = 0, + DDR3_MR1_RTT_NOM_RZQ4 = 1, + DDR3_MR1_RTT_NOM_RZQ2 = 2, + DDR3_MR1_RTT_NOM_RZQ6 = 3, + DDR3_MR1_RTT_NOM_RZQ12 = 4, + DDR3_MR1_RTT_NOM_RZQ8 = 5, +}; +enum ddr3_mr1_additive_latency { + DDR3_MR1_AL_DISABLE = 0, + DDR3_MR1_AL_CL_MINUS_1 = 1, + DDR3_MR1_AL_CL_MINUS_2 = 2, +}; +enum ddr3_mr1_ods { + DDR3_MR1_ODS_RZQ6 = 0, + DDR3_MR1_ODS_RZQ7 = 1, +}; +enum ddr3_mr1_dll { + DDR3_MR1_DLL_ENABLE = 0, + DDR3_MR1_DLL_DISABLE = 1, +}; +/** + * \brief Get command address for a DDR3 MR1 command + */ +mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, + enum ddr3_mr1_tqds tqds, + enum ddr3_mr1_rtt_nom rtt_nom, + enum ddr3_mr1_write_leveling write_leveling, + enum ddr3_mr1_ods output_drive_strenght, + enum ddr3_mr1_additive_latency additive_latency, + enum ddr3_mr1_dll dll_disable +); + +enum ddr3_mr2_rttwr { + DDR3_MR2_RTTWR_OFF = 0, + DDR3_MR2_RTTWR_RZQ4 = 1, + DDR3_MR2_RTTWR_RZQ2 = 2, +}; +enum ddr3_mr2_srt_range { + DDR3_MR2_SRT_NORMAL = 0, + DDR3_MR2_SRT_EXTENDED = 1, +}; +enum ddr3_mr2_asr { + DDR3_MR2_ASR_MANUAL = 0, + DDR3_MR2_ASR_AUTO = 1, +}; +/** + * \brief Get command address for a DDR3 MR2 command + */ +mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, + enum ddr3_mr2_srt_range extended_temp, + enum ddr3_mr2_asr self_refresh, + u8 cas_cwl +); + +/** + * \brief Get command address for a DDR3 MR3 command + */ +mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr); + +#endif /* REDUNDANT_H */ \ No newline at end of file diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c new file mode 100644 index 0000000..761a162 --- /dev/null +++ b/src/northbridge/via/vx900/early_host_bus_ctl.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include "early_vx900.h" + +static void vx900_cpu_bus_preram_setup(void) +{ + pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08); + + /* */ + pci_mod_config8(HOST_BUS, 0x51, 0, (1<<5) | (1<<3) | (1<<2) | (1<<6) ); + + pci_write_config8(HOST_BUS, 0x52, 0xc7); + + /* High priority upstream requests on V4 bus */ + pci_write_config8(HOST_BUS, 0x56, 0x03); + /* CPU to DRAM extra 1T access control */ + pci_mod_config8(HOST_BUS, 0x59, 0x00, 1<<2); + /* Queue reordering */ + pci_mod_config8(HOST_BUS, 0x5f, 0x00, 1<<6); + /* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */ + pci_mod_config8(HOST_BUS, 0x98, 0x00, 0x60); + /* 1T delay for data on CPU bus */ + pci_write_config8(HOST_BUS, 0x9e, 0x0e); + /* Arbitrate ownership of DRAM controller a few cycles earlier */ + pci_mod_config8(HOST_BUS, 0x9f, 0x00, 1<<7); + /* Write retire policy */ + pci_write_config8(HOST_BUS, 0x5d, 0xa2); + /* Occupancy timer */ + pci_write_config8(HOST_BUS, 0x53, 0x44); + /* Medium Threshold for Write Retire Policy - 6 requests */ + pci_mod_config8(HOST_BUS, 0x56, 0x00, 0x60); + /* Bandwidth timer */ + pci_write_config8(HOST_BUS, 0x5e, 0x44); +} + +void vx900_cpu_bus_slowest_rdry(void) +{ + /* Disable fast CPU to DRAM cycle, otherwise we might hang on raminit */ + pci_mod_config8(HOST_BUS, 0x51, 1<<7, 0); + /* Memory to CPU synchronous mode */ + pci_mod_config8(HOST_BUS, 0x51, 1<<1, 0); +} + +void vx900_cpu_bus_interface_setup(void) +{ + /* Enable 8QW burst and 4QW request merging [4] and [2] + * and special mode for read cycles bit[3] */ + //pci_mod_config8(HOST_BUS, 0x54, 0, (1<<4) | (1<<2) | (1<<3) ); + + /* This is good practice to do before raminit */ + //vx900_cpu_bus_slowest_rdry(); + + vx900_cpu_bus_preram_setup(); + + dump_pci_device(HOST_BUS); +} \ No newline at end of file diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c new file mode 100644 index 0000000..17bf573 --- /dev/null +++ b/src/northbridge/via/vx900/early_smbus.c @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <device/pci_ids.h> +#include "early_vx900.h" +#include <device/early_smbus.h> + +#include <arch/io.h> +#include <console/console.h> + +/** + * \brief SMBUS IO ports in relation to the base IO port + */ +#define SMBHSTSTAT(base) (u16)(u32)base + 0x0 +#define SMBSLVSTAT(base) (u16)(u32)base + 0x1 +#define SMBHSTCTL(base) (u16)(u32)base + 0x2 +#define SMBHSTCMD(base) (u16)(u32)base + 0x3 +#define SMBXMITADD(base) (u16)(u32)base + 0x4 +#define SMBHSTDAT0(base) (u16)(u32)base + 0x5 +#define SMBHSTDAT1(base) (u16)(u32)base + 0x6 +#define SMBBLKDAT(base) (u16)(u32)base + 0x7 +#define SMBSLVCTL(base) (u16)(u32)base + 0x8 +#define SMBTRNSADD(base) (u16)(u32)base + 0x9 +#define SMBSLVDATA (base) (u16)(u32)base + 0xa + + +__attribute__((unused)) +static void smbus_delays(int delays) +{ + while(delays--) smbus_delay(); +} + + +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) +{ + u8 val; + + /* Initialize SMBUS sequence */ + smbus_reset(smbus_dev); + /* Clear host data port. */ + outb(0x00, SMBHSTDAT0(smbus_dev)); + + smbus_wait_until_ready(smbus_dev); + smbus_delays(50); + + /* Actual addr to reg format. */ + addr = (addr << 1); + addr |= 1; /* read command */ + outb(addr, SMBXMITADD(smbus_dev)); + outb(offset, SMBHSTCMD(smbus_dev)); + /* Start transaction, byte data read. */ + outb(0x48, SMBHSTCTL(smbus_dev)); + smbus_wait_until_ready(smbus_dev); + + val = inb(SMBHSTDAT0(smbus_dev)); + return val; +} + +void enable_smbus(void) +{ + device_t dev; + u8 reg8; + u32 smbus_dev = (u32)SMBUS_IO_BASE; + + /* Locate the Power Management control */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_LPC), 0); + + if (dev == PCI_DEV_INVALID) { + die("Power Management Controller not found\n"); + } + + /* + * To use SMBus to manage devices on the system board, it is a must to + * enable SMBus function by setting + * PMU_RXD2[0] (SMBus Controller Enable) to 1. + * And set PMU_RXD0 and PMU_RXD1 (SMBus I/O Base) to an appropriate + * I/O port address, so that all registers in SMBus I/O port can be + * accessed. + */ + + reg8 = pci_read_config8(dev, 0xd2); + /* Enable SMBus controller */ + reg8 |= 1; + /* Set SMBUS clock from 128k source */ + reg8 |= 1<<2; + pci_write_config8(dev, 0xd2, reg8); + + reg8 = pci_read_config8(dev, 0x94); + /* SMBUS clock from divider of 14.318 MHz */ + reg8 &= ~(1<<7); + pci_write_config8(dev, 0x94, reg8); + + /* Set SMBus IO base */ + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE); + + /* + * Initialize the SMBus sequence: + */ + /* Clear SMBus host status register */ + smbus_reset(smbus_dev); + /* Clear SMBus host data 0 register */ + outb(0x00, SMBHSTDAT0(smbus_dev)); + + /* Wait for SMBUS */ + smbus_wait_until_ready(smbus_dev); + +} + +void spd_read(u8 addr, spd_raw_data spd) +{ + u8 reg; + int i, regs; + u32 smbus_dev = SMBUS_IO_BASE; + + reg = smbus_read_byte(smbus_dev, addr, 2); + if(reg != 0x0b) + { + printk(BIOS_DEBUG, "SMBUS device %x not a DDR3 module\n", addr); + spd[2] = 0; + return; + } + + reg = smbus_read_byte(smbus_dev, addr, 0); + reg &= 0xf; + if (reg == 0x3) { + regs = 256; + } else if (reg == 0x2) { + regs = 176; + } else if (reg == 0x1) { + regs = 128; + } else { + printk(BIOS_INFO, "No DIMM present at %x\n", addr); + spd[2] = 0; + return; + } + printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", addr); + for (i = 0; i < regs; i++) { + reg = smbus_read_byte(smbus_dev, addr, i); + //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", i, reg ); + spd[i] = reg; + } +} + +void dump_spd_data(void) +{ + int dimm, offset, regs; + unsigned int reg; + spd_raw_data spd; + dimm_attr dimmx; + u32 smbus_dev = (u32 )SMBUS_IO_BASE; + + for (dimm = 0x50; dimm < 0x52; dimm++) { + reg = smbus_read_byte(smbus_dev, dimm, 2); + if(reg != 0x0b) + { + printk(BIOS_DEBUG, + "SMBUS device %x not a DDR3 module\n", dimm); + continue; + } + + reg = smbus_read_byte(smbus_dev, dimm, 0); + reg &= 0xf; + if (reg == 0x3) { + regs = 256; + } else if (reg == 0x2) { + regs = 176; + } else if (reg == 0x1) { + regs = 128; + } else { + printk(BIOS_INFO, "No DIMM present at %x\n", dimm); + regs = 0; + continue; + } + printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", dimm); + for (offset = 0; offset < regs; offset++) { + reg = smbus_read_byte(smbus_dev, dimm, offset); + //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", offset, reg ); + spd[offset] = reg; + } + + spd_decode_ddr3(&dimmx, spd); + dram_print_spd_ddr3(&dimmx); + + } +} + diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c new file mode 100644 index 0000000..c03a548 --- /dev/null +++ b/src/northbridge/via/vx900/early_vx900.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include "early_vx900.h" +#include <arch/io.h> +#include <console/console.h> + +unsigned long get_top_of_ram(void) +{ + u16 reg_tom = pci_read_config8(MCU, 0x88); + return (((unsigned long) reg_tom) << 24) - (256<<20); +} + +struct cbmem_entry *get_cbmem_toc(void) +{ + return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); +} + +void vx900_enable_pci_config_space(void) +{ + /* MMCONF is not yet enabled, so we'll need to specify we want to do + * pci_io. We don't want to do pci_mmio until we enable it */ + /* Enable multifunction bit for northbridge. + * This enables the PCI configuration spaces of D0F1 to D0F7 to be + * accessed */ + pci_io_write_config8(HOST_CTR, 0x4f, 0x01); + +#if CONFIG_MMCONF_SUPPORT + /* COOL, now enable MMCONF */ + u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); + reg8 |= 3; + pci_io_write_config8(TRAF_CTR, 0x60, reg8); + reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; + pci_io_write_config8(TRAF_CTR, 0x61, reg8); +#endif +} + +/** + *\brief Prints information regarding the hardware strapping on VX900 + * + * Certain features on the VX900 are controlled by strapping pins which are + * hardwired on the mainboard. These values determine whether the ROM is on the + * SPI or LPC bus, or whether auto-reset is enabled. + * \n + * Having a feel for these values is important when trying to fix obscure + * problems found when porting a mainboard based on the VX900. + * \n + * These values are decoded and printed to the terminal. + */ +void vx900_print_strapping_info(void) +{ + u8 strap = pci_read_config8(SNMIC, 0x56); + + print_debug("VX900 strapping pins indicate that:\n"); + printk(BIOS_DEBUG, " ROM is on %s bus\n", + (strap & (1<<0)) ? "SPI" : "LPC" ); + printk(BIOS_DEBUG, " Auto reset is %s\n", + (strap & (1<<1)) ? "disabled" : "enabled" ); + printk(BIOS_DEBUG, " LPC FWH command is %s\n", + (strap & (1<<2)) ? "enabled" : "disabled" ); + printk(BIOS_DEBUG, " Debug link is is %s\n", + (strap & (1<<4)) ? "enabled" : "disabled" ); + printk(BIOS_DEBUG, " PCI master mode is %s\n", + (strap & (1<<5)) ? "enabled" : "disabled" ); +} + +/** + *\brief Disables the auto-reboot mechanism on VX900 + * + * The VX900 has an auto-reboot mechanism that can be enabled by a hardware + * strap. This mechanism can make development annoying, since we don't know if + * the reset was caused by a bug in coreboot, or by this mechanism. + */ +void vx900_disable_auto_reboot(void) +{ + if( pci_read_config8(SNMIC, 0x56) & (1<<1) ) { + print_debug("Auto-reboot is disabled in hardware\n"); + return; + } + /* Disable the GP3 timer, which is the root of all evil */ + pci_write_config8(LPC, 0x98, 0); + /* Yep, that's all it takes */ + print_debug("GP3 timer disabled." + " Auto-reboot should not give you any more trouble.\n"); +} + +void vx900_disable_legacy_rom_shadow(void) +{ + /* Disable shitty 8086 legacy shadows + * This frees the entire 640k-1M range for DRAM + * VGA may still use 640k-768k if enabled later + * Unfortunately, we need to disable these shadows in more than one + * device, and that's why some ranges are disabled more than once */ + pci_write_config8(MCU, 0x80, 0xff); /* ROM 768k - 832k */ + pci_write_config8(MCU, 0x81, 0xff); /* ROM 832k - 896k */ + pci_write_config8(MCU, 0x82, 0xff); /* ROM 896k - 960k */ + /* ROM 960k - 1M * SMRAM: 640k - 768k */ + pci_write_config8(MCU, 0x83, 0x31); + + /* Bits 6:0 are the ROM shadow on top of 4G, so leave those untouched */ + pci_mod_config8(LPC, 0x41, 1<<7, 0);/* 896k - 960k */ + + pci_write_config8(SNMIC, 0x61, 0); /* 768k - 832k */ + pci_write_config8(SNMIC, 0x62, 0); /* 832k - 896k */ + pci_write_config8(SNMIC, 0x63, 0); /* 896k - 1M */ + pci_write_config8(SNMIC, 0x64, 0); /* 896k - 960k */ + + /* Doesn't really belong here, but it is "shitty legacy" + * Enable A20 line */ + outb( inb(0x92)|(1<<1), 0x92); +} + +void vx900_disable_gfx(void) +{ + /* Disable GFX */ + pci_mod_config8(MCU, 0xa1, 1<<7, 0); +} diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h new file mode 100644 index 0000000..7fa41f8 --- /dev/null +++ b/src/northbridge/via/vx900/early_vx900.h @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef EARLY_VX900_H +#define EARLY_VX900_H + +#include "raminit.h" +#include "vx900.h" + +#include <arch/io.h> +#include <cbmem.h> +//#include <devices/smbus/smbus.h> +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> + +/* North Module devices */ +#define HOST_CTR PCI_DEV(0, 0, 0) +#define ERR_REP PCI_DEV(0, 0, 1) +#define HOST_BUS PCI_DEV(0, 0, 2) +#define MCU PCI_DEV(0, 0, 3) +#define POWERMAN PCI_DEV(0, 0, 4) +#define TRAF_CTR PCI_DEV(0, 0, 5) +#define NSBIC PCI_DEV(0, 0, 7) + +#define GFX PCI_DEV(0, 1, 0) +#define HDMI PCI_DEV(0, 1, 0) + +#define PEXx PCI_DEV(0, 3, x) +#define PEX_CTR PCI_DEV(0, 3, 4) + +/* South Module devices */ +#define UARTx PCI_DEV(0, 0x0a, x) +#define USB_MASS PCI_DEV(0, 0x0b, 0) +#define SDIO PCI_DEV(0, 0x0c, 0) +#define CARD_RD PCI_DEV(0, 0x0d, 0) +#define SATA PCI_DEV(0, 0x0d, 0) +#define USBx PCI_DEV(0, 0x10, x) +#define USB_EHCI PCI_DEV(0, 0x10, 4) +#define LPC PCI_DEV(0, 0x11, 0) +#define PMU LPC +#define SNMIC PCI_DEV(0, 0x11, 7) +#define P2P PCI_DEV(0, 0x13, 0) +#define HDAC PCI_DEV(0, 0x14, 0) + + +unsigned long get_top_of_ram(void); + +void enable_smbus(void); +void dump_spd_data(void); +void spd_read(u8 addr, spd_raw_data spd); + +void vx900_enable_pci_config_space(void); +void vx900_disable_legacy_rom_shadow(void); + +void vx900_print_strapping_info(void); +void vx900_disable_auto_reboot(void); + +void vx900_cpu_bus_slowest_rdry(void); +void vx900_cpu_bus_interface_setup(void); + +void vx900_dram_set_gfx_resources(void); +void vx900_disable_gfx(void); + +static inline void dump_pci_device(device_t dev) +{ + int i; + printram("PCI: %.2x:%.2x.%.2x", + (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7 ); + printram("\n"); + + for (i = 0; i <= 0xff; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + printram("%.2x:", i); + } + + if ((i & 0x0f) == 0x08) { + printram(" |"); + } + + val = pci_read_config8(dev, i); + printram(" %.2x", val); + + if ((i & 0x0f) == 0x0f) { + printram("\n"); + } + } +} +#endif /* EARLY_VX900_H */ diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c new file mode 100644 index 0000000..6e4eec1 --- /dev/null +++ b/src/northbridge/via/vx900/lpc.c @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/i8259.h> +#include <pc80/mc146818rtc.h> +#include <drivers/generic/ioapic/chip.h> + +#include "vx900.h" +#include "chip.h" + +static void vx900_lpc_misc_stuff(device_t dev) +{ + char extint; + u8 val; + struct northbridge_via_vx900_config *nb = (void*)dev->chip_info; + + /* GPIO 11,10 to SATALED [1,0] */ + pci_mod_config8(dev, 0xe4, 0 , 1<<0); + + /* Route the external interrupt line */ + extint = nb->ext_int_route_to_pirq; + if (extint < 'A' || extint > 'H') { + printk(BIOS_WARNING, "Invalid PIRQ%c for external interrupt\n", + extint); + } else { + printk(BIOS_INFO, "Routing external interrupt to PIRQ%c\n", + extint); + val = extint - 'A'; + val |= (1 << 3); /* bit3 enables the external int */ + pci_mod_config8(dev, 0x55, 0xf, val); + + } +} + +static void vx900_lpc_dma_setup(device_t dev) +{ + /* These are the steps recommended by VIA in order to get DMA running */ + + /* Enable Positive South Module PCI Cycle Decoding */ + /* FIXME: Setting this seems to hang our system */ + //pci_mod_config8(dev, 0x58, 0, 1<<4); + /* Positive decoding for ROM + APIC + On-board IO ports */ + pci_mod_config8(dev, 0x6c, 0, (1<<2) | (1<<3) | (1<<7)); + /* Enable DMA channels. BIOS guide recommends DMA channel 2 off */ + pci_write_config8(dev, 0x53, 0xfb); + /* Disable PCI/DMA Memory Cycles Output to PCI Bus */ + pci_mod_config8(dev, 0x5b, (1<<5), 0); + /* DMA bandwidth control - Improved bandwidth */ + pci_write_config8(dev, 0x53, 0xff); + /* ISA Positive Decoding control */ + pci_write_config8(dev, 0x6d, 0xdf); + pci_write_config8(dev, 0x6e, 0x98); + pci_write_config8(dev, 0x6f, 0x30); +} + +/** + *\brief VX900: Set up the south module IOAPIC (for the ISA/LPC bus) + * + * Enable the IOAPIC in the south module, and properly set it up. + * \n + * This is the hardware specific initialization for the IOAPIC, and complements + * the setup done by the generic IOAPIC driver. In order for the IOAPIC to work + * properly, it _must_ be declared in devicetree.cb . + * \n + * We are assuming this is called before the drivers/generic/ioapic code, + * which should be the case if devicetree.cb is set up properly. + */ +static void vx900_lpc_ioapic_setup(device_t dev) +{ + /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb + * If it's not, then the generic ioapic driver will not set it up + * correctly, and the MP table will not be correctly generated */ + device_t ioapic; + for(ioapic = dev->next; ioapic; ioapic = ioapic->next) + { + if(ioapic->path.type == DEVICE_PATH_IOAPIC) + break; + } + + /* You did put an IOAPIC in devicetree.cb, didn't you? */ + if(ioapic == 0) { + /* We don't have enough info to set up the IOAPIC */ + printk(BIOS_ERR, "ERROR: South module IOAPIC not found. " + "Check your devicetree.cb\n"); + return; + } + + /* Found an IOAPIC, now we need to make sure it's the right one */ + ioapic_config_t *config = (ioapic_config_t*)ioapic->chip_info; + if(!config->have_isa_interrupts) { + /* Umh, is this the right IOAPIC ? */ + printk(BIOS_ERR, "ERROR: South module IOAPIC not carrying ISA " + "interrupts. Check your devicetree.cb\n"); + printk(BIOS_ERR, "Will not initialize this IOAPIC.\n"); + return; + } + + /* The base address of this IOAPIC _must_ be at 0xfec00000. + * Don't move this value to a #define, as people might think it's + * configurable. It is not. */ + const u32 base = config->base; + if(base != 0xfec00000) { + printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at " + "0xfec00000\n but we found it at 0x%.8x\n", + base); + return; + } + + print_debug("VX900 LPC: Setting up the south module IOAPIC.\n"); + /* Enable IOAPIC + * So much work for one line of code. Talk about bloat :) + * The 8259 PIC should still work even if the IOAPIC is enabled, so + * there's no crime in enabling the IOAPIC here. */ + pci_mod_config8(dev, 0x58, 0, 1<<6); +} + +static void vx900_lpc_interrupt_stuff(device_t dev) +{ + /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports + * And enable I/O recovery time */ + pci_mod_config8(dev, 0x40, 0, (1<<2)|(1<<6)); + /* Set serial IRQ frame width to 6 PCI cycles (recommended by VIA) + * And enable serial IRQ */ + pci_mod_config8(dev, 0x52, 3<<0, (1<<3)|(1<<0) ); + + /* Disable IRQ12 storm FIXME: bad comment */ + pci_mod_config8(dev, 0x51, (1<<2), 0); + + pci_write_config8(dev, 0x4c, (1<<6) ); + + /* Get the IRQs up and running. SeaBIOS/linux needs these to boot */ + setup_i8259(); + + vx900_lpc_dma_setup(dev); + + /* The IOAPIC is special, and we treat it separately */ + vx900_lpc_ioapic_setup(dev); +} + +static void dump_pci_device(device_t dev) +{ + int i; + for (i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + if((i & 7) == 0) print_debug(" |"); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} + +static void vx900_lpc_init(device_t dev) +{ + vx900_lpc_interrupt_stuff(dev); + vx900_lpc_misc_stuff(dev); + dump_pci_device(dev); +} + +static struct device_operations vx900_lpc_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vx900_lpc_init, + .scan_bus = scan_static_bus, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &vx900_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_LPC, +}; + +#if CONFIG_PIRQ_ROUTE +void pirq_assign_irqs(const u8* pirq) +{ + device_t lpc; + + lpc = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_LPC, 0); + + /* Take care of INTA -> INTD */ + pci_mod_config8(lpc, 0x55, (0xf << 4), pirq[0] << 4); + pci_write_config8(lpc, 0x56, pirq[1] | (pirq[2] << 4) ); + pci_write_config8(lpc, 0x57, pirq[3] << 4); + + /* Enable INTE -> INTH to be on separate IRQs */ + pci_mod_config8(lpc, 0x46, 0, 1<<4); + /* Now do INTE -> INTH */ + pci_write_config8(lpc, 0x44, pirq[4] | (pirq[5] << 4) ); + pci_write_config8(lpc, 0x45, pirq[6] | (pirq[7] << 4) ); +} +#endif diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c new file mode 100644 index 0000000..d55ed2b --- /dev/null +++ b/src/northbridge/via/vx900/northbridge.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include "vx900.h" +#include "chip.h" + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cbmem.h> +#include <lib.h> +#include <reset.h> +#include <string.h> + +void hard_reset(void) +{ + outb((1 << 2) | (1 << 1), 0xcf9); +} + +static void vx900_set_resources(device_t dev) +{ + print_debug("========================================" + "========================================\n"); + print_debug("============= VX900 memory sizing & Co. " + "========================================\n"); + print_debug("========================================" + "========================================\n"); + + int idx = 10; + const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, + 0); + if (!mcu) { + die("Something is terribly wrong.\n" + " We tried locating the MCU on the PCI bus, " + "but couldn't find it. Halting.\n"); + } + + u32 pci_tolm = find_pci_tolm(dev->link_list); + printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm); + printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm >> 20); + + /* The last valid DRAM address is computed by the MCU + * One issue might be if we have a hole in the rank mappings, so that + * virtual ranks are not mapped successively in the linear address space + * (Ex: rank 0 mapped 0-1G, rank 1 mapped 2G-3G) + * We don't do this awkward mapping in RAM init, so we don't worry about + * it here, but it is something to keep in mind if having RAM issues */ + u32 vx900_tom = pci_read_config16(mcu, 0x88) & 0x07ff; + const u32 tomk = vx900_tom << (24 - 10); + printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk >> 10); + + /* Do the same for top of low RAM */ + u32 vx900_tolm = (pci_read_config16(mcu, 0x84) & 0xfff0) >> 4; + u32 full_tolmk = vx900_tolm << (20 - 10); + /* FIXME: Remap above 4G */ + full_tolmk = min(full_tolmk, pci_tolm >> 10); + printk(BIOS_SPEW, "Found top of low memory at %dMB\n", + full_tolmk >> 10); + + /* What about the framebuffer for the integrated GPU? */ + u32 fbufk = chrome9hd_fb_size() >> 10; + printk(BIOS_SPEW, "Integrated graphics buffer: %dMB\n", fbufk >> 10); + + /* Can't use the framebuffer as system RAM, sorry */ + u32 tolmk = full_tolmk - fbufk; + ram_resource(dev, idx++, 0, 640); + printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10); + /* FIXME: how can we avoid leaving this hole? + * Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */ + /* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem + * to be always mapped to the top of 1M, but this can be overcome with + * some smart positive/subtractive resource decoding */ + ram_resource(dev, idx++, 768, (tolmk - 768)); + uma_memory_size = fbufk << 10; + uma_memory_base = tolmk << 10; + + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk << 10) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", + high_tables_base, high_tables_size); + /* Because of the video framebuffer, the high tables may be in a + * different location than in romstage, so we need to copy them over */ +/* void* old_tables = (void*)((full_tolmk<<10) - HIGH_MEMORY_SIZE); + void* new_tables = (void*)((u32)high_tables_base); + printk(BIOS_DEBUG, "Moving CBMEM from %p to %p\n", + old_tables, new_tables); + memcpy(new_tables, old_tables, HIGH_MEMORY_SIZE); + cbmem_reinit(high_tables_base);*/ + + print_debug("======================================================\n"); + assign_resources(dev->link_list); +} + +static void vx900_read_resources(device_t dev) +{ + /* Our fixed resources start at 0 */ + int idx = 0; + /* Reserve our ROM mapped space */ + struct resource *res; + res = new_resource(dev, idx++); + res->size = 512 * KiB; + res->base = 0xffffffff - (res->size - 1); + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Now do the same for our MMCONF */ + res = new_resource(dev, idx++); + res->size = 256 * MiB; + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + pci_domain_read_resources(dev); +} + +static struct device_operations pci_domain_ops = { + .read_resources = vx900_read_resources, + .set_resources = vx900_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_via_vx900_ops = { + CHIP_NAME("VIA VX900 Chipset") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c new file mode 100644 index 0000000..c9b04eb --- /dev/null +++ b/src/northbridge/via/vx900/pcie.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> + +static void dump_pci_device(device_t dev) +{ + int i; + for (i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + if ((i & 7) == 0) + print_debug(" |"); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} + +static void vx900_pcie_link_init(device_t dev) +{ + u8 reg8; + u32 reg32; + + u8 fn = dev->path.pci.devfn & 0x07; + + /* Step 1 : Check for presence of PCIE device */ + reg8 = pci_read_config8(dev, 0x5a); + + if (reg8 & (1 << 6) ) + printk(BIOS_DEBUG, "Card detected in PEX%i\n", fn); + else + return; + + /* Step 2: Wait for device to enter L0 state */ + while (0x8a != pci_read_config8(dev, 0x1c3)); + + /* Step 3: Clear PCIe error status, then check for failures */ + pci_write_config32(dev, 0x104, 0xffffffff); + reg32 = pci_read_config32(dev, 0x104); + if (0 != reg32) { + printk(BIOS_DEBUG, "PEX init error. flags 0x%.8x\n", reg32); + return; + } + + pci_write_config32(dev, 0x110, 0xffffffff); + reg32 = pci_read_config32(dev, 0x110); + if (0 != reg32) + printk(BIOS_DEBUG, "PEX errors. flags 0x%.8x\n", reg32); + + pci_write_config8(dev, 0xa4, 0xff); + if (pci_read_config8(dev, 0x4a) & (1 << 3)) + print_debug("Unsupported request detected.\n"); + + pci_write_config8(dev, 0x15a, 0xff); + if (pci_read_config8(dev, 0x15a) & (1 << 1)) + print_debug("Negotiation pending.\n"); + + /* Step 4: Read vendor ID */ + +} + +static void vx900_pex_dev_set_resources(device_t dev) +{ + //print_debug("======================================================\n"); + //print_debug("== PEX set\n"); + //print_debug("======================================================\n"); + + assign_resources(dev->link_list); +} + +static void vx900_pex_init(device_t dev) +{ + //print_debug("======================================================\n"); + //print_debug("== PEX init\n"); + //print_debug("======================================================\n"); + + if ((dev->path.pci.devfn & 0x7) == 0) + return; + vx900_pcie_link_init(dev); + + if (0) dump_pci_device(dev); +} + +static struct device_operations vx900_pex_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = vx900_pex_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = vx900_pex_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, +}; + +static const struct pci_driver pex1_driver __pci_driver = { + .ops = &vx900_pex_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_PEX1, +}; + +static const struct pci_driver pex2_driver __pci_driver = { + .ops = &vx900_pex_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_PEX2, +}; + +static const struct pci_driver pex3_driver __pci_driver = { + .ops = &vx900_pex_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_PEX3, +}; + +static const struct pci_driver pex4_driver __pci_driver = { + .ops = &vx900_pex_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_PEX4, +}; diff --git a/src/northbridge/via/vx900/raminit.h b/src/northbridge/via/vx900/raminit.h new file mode 100644 index 0000000..c599c0f --- /dev/null +++ b/src/northbridge/via/vx900/raminit.h @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef RAMINIT_VX900_H +#define RAMINIT_VX900_H + +#include <device/dram/ddr3.h> +#include "vx900.h" + +#define SPD_END_LIST 0xff + +typedef struct dimm_layout_st +{ + /* The address of the DIMM on the SMBUS * + * 0xFF to terminate the array*/ + u8 spd_addr[VX900_MAX_DIMM_SLOTS + 1]; +} dimm_layout; + +typedef struct dimm_info_st +{ + dimm_attr dimm[VX900_MAX_DIMM_SLOTS]; +} dimm_info; + +typedef struct mem_rank_st { + u16 start_addr; + u16 end_addr; +} mem_rank; + +typedef struct rank_layout_st { + u32 phys_rank_size_mb[VX900_MAX_MEM_RANKS]; + mem_rank virt[VX900_MAX_MEM_RANKS]; + dimm_flags_t flags[VX900_MAX_MEM_RANKS]; +} rank_layout; + +typedef struct pci_reg8_st { + u8 addr; + u8 val; +} pci_reg8; + +typedef u8 timing_dly[8]; + +typedef struct delay_range_st { + timing_dly low; + timing_dly avg; + timing_dly high; +} delay_range; + +typedef struct vx900_delay_calib_st { + delay_range rx_dq_cr; + delay_range rx_dqs; + /* Transmit delays are calibrated for each dimm */ + delay_range tx_dq[VX900_MAX_DIMM_SLOTS]; + delay_range tx_dqs[VX900_MAX_DIMM_SLOTS]; +} vx900_delay_calib; + +typedef struct ramctr_timing_st { + enum spd_memory_type dram_type; + u16 cas_supported; + /* tLatencies are in units of ns, scaled by x256 */ + u32 tCK; + u32 tAA; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tFAW; + /* Latencies in terms of clock cycles + * They are saved separately as they are needed for DRAM MRS commands*/ + u8 CAS; /* CAS read latency */ + u8 CWL; /* CAS write latency */ + u8 WR; /* write recovery time */ + /* Number of dimms currently connected */ + u8 n_dimms; + +} ramctr_timing; + +void vx900_init_dram_ddr3(const dimm_layout *dimms); + +#endif /* RAMINIT_VX900_H */ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c new file mode 100644 index 0000000..6677ace --- /dev/null +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -0,0 +1,1440 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include "early_vx900.h" +#include "raminit.h" +#include <arch/io.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <delay.h> +#include <lib.h> +#include <string.h> + +/* Map BA0 <-> A17, BA1 <-> A18 */ +/* Map BA2 <-> A19, RA0/RA1 must not overlap BA[0:2] */ +#define VX900_MRS_MA_MAP 0x4b33 /* MA Pin Mapping for MRS commands */ +#define VX900_CALIB_MA_MAP 0x5911 /* MA Pin mapping for calibrations */ + +/* Registers 0x78 -> 0x7f contain calibration the settings for DRAM IO timing + * The dataset in these registers is selected from 0x70. + * Once the correct dataset is selected the delays can be altered. + * delay_type refers to TxDQS, TxDQ, RxDQS, or RxCR + * bound refers to either manual, average, upper bound, or lower bound + */ +#define CALIB_TxDQS 0 +#define CALIB_TxDQ 1 +#define CALIB_RxDQS 2 +#define CALIB_RxDQ_CR 3 + +#define CALIB_AVERAGE 0 +#define CALIB_LOWER 1 +#define CALIB_UPPER 2 +#define CALIB_MANUAL 4 + +static void vx900_delay_calib_mode_select(u8 delay_type, u8 bound) +{ + /* Which calibration setting */ + u8 reg8 = (delay_type & 0x03) << 2; + /* Upper, lower, average, or manual setting */ + reg8 |= (bound & 0x03); + pci_write_config8(MCU, 0x70, reg8); +} + +static void vx900_read_0x78_0x7f(timing_dly dly) +{ + *((u32 *) (&(dly[0]))) = pci_read_config32(MCU, 0x78); + *((u32 *) (&(dly[4]))) = pci_read_config32(MCU, 0x7c); +} + +static void vx900_write_0x78_0x7f(const timing_dly dly) +{ + pci_write_config32(MCU, 0x78, *((u32 *) (&(dly[0])))); + pci_write_config32(MCU, 0x7c, *((u32 *) (&(dly[4])))); +} + +static void vx900_read_delay_range(delay_range * d_range, u8 mode) +{ + vx900_delay_calib_mode_select(mode, CALIB_LOWER); + vx900_read_0x78_0x7f(d_range->low); + vx900_delay_calib_mode_select(mode, CALIB_AVERAGE); + vx900_read_0x78_0x7f(d_range->avg); + vx900_delay_calib_mode_select(mode, CALIB_UPPER); + vx900_read_0x78_0x7f(d_range->high); +} + +static void dump_delay(const timing_dly dly) +{ + u8 i; + for (i = 0; i < 8; i++) { + printram(" %.2x", dly[i]); + } + printram("\n"); +} + +static void dump_delay_range(const delay_range d_range) +{ + printram("Lower limit: "); + dump_delay(d_range.low); + printram("Average: "); + dump_delay(d_range.avg); + printram("Upper limit: "); + dump_delay(d_range.high); +} + +/* These are some "safe" values that can be used for memory initialization. + * Some will stay untouched, and others will be overwritten later on + * YOU REALLY NEED THE DATASHEET TO UNDERSTAND THESE !!! */ +static pci_reg8 mcu_init_config[] = { + {0x40, 0x01}, /* Virtual rank 0 ending address = 64M - 1 */ + {0x41, 0x00}, {0x42, 0x00}, {0x43, 0x00}, /* Virtual Ranks ending */ + {0x48, 0x00}, /* Virtual rank 0 starting address = 0 */ + {0x49, 0x00}, {0x4a, 0x00}, {0x4b, 0x00}, /* Virtual Ranks beginning */ + {0x50, 0xd8}, /* Set ranks 0-3 to 11 col bits, 16 row bits */ + /* Disable all virtual ranks */ + {0x54, 0x00}, {0x55, 0x00}, {0x56, 0x00}, {0x57, 0x00}, + /* Disable rank interleaving in ranks 0-3 */ + {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x00}, {0x5b, 0x00}, + {0x6c, 0xA0}, /* Memory type: DDR3, VDIMM: 1.5V, 64-bit DRAM */ + {0xc4, 0x80}, /* Enable 8 memory banks */ + {0xc6, 0x80}, /* Minimum latency from self-refresh. Bit [7] must be 1 */ + /* FIXME: do it here or in Final config? */ + {0xc8, 0x80}, /* Enable automatic triggering of short ZQ calibration */ + {0x99, 0xf0}, /* Power Management and Bypass Reorder Queue */ + /* Enable differential DQS; MODT assertion values suggested in DS */ + {0x9e, 0xa1}, {0x9f, 0x51}, + /* DQ/DQM Duty Control - Do not put any extra delays */ + {0xe9, 0x00}, {0xea, 0x00}, {0xeb, 0x00}, {0xec, 0x00}, + {0xed, 0x00}, {0xee, 0x00}, {0xef, 0x00}, + {0xfc, 0x00}, {0xfd, 0x00}, {0xfe, 0x00}, {0xff, 0x00}, + /* The following parameters we may or may not change */ + {0x61, 0x2e}, /* DRAMC Pipeline Control */ + {0x77, 0x10}, /* MDQS Output Control */ + + /* The following are parameters we'll most likely never change again */ + {0x60, 0xf4}, /* DRAM Pipeline Turn-Around Setting */ + {0x65, 0x49}, /* DRAM Arbitration Bandwidth Timer - I */ + {0x66, 0x80}, /* DRAM Queue / Arbitration */ + {0x69, 0xc6}, /* Bank Control: 8 banks, high priority refresh */ + {0x6a, 0xfc}, /* DRAMC Request Reorder Control */ + {0x6e, 0x38}, /* Burst lenght: 8, burst-chop: enable */ + {0x73, 0x04}, /* Close All Pages Threshold */ + + /* The following need to be dynamically asserted */ + /* See: check_special_registers.c */ + {0x74, 0xa0}, /* Yes, same 0x74; add one more T */ + {0x76, 0x60}, /* Write Data Phase Control */ + +}; + +/* This table keeps the driving strength control setting that we can safely use + * doring initialization. */ +static pci_reg8 mcu_drv_ctrl_config[] = { + {0xd3, 0x03}, /* Enable auto-compensation circuit for ODT strength */ + {0xd4, 0x80}, /* Set internal ODT to dynamically turn on or off */ + {0xd6, 0x20}, /* Enable strong driving for MA and DRAM commands */ + {0xd0, 0x88}, /* (ODT) Strength ?has effect? */ + {0xe0, 0x88}, /* DRAM Driving – Group DQS (MDQS) */ + {0xe1, 0x00}, /* Disable offset mode for driving strength control */ + {0xe2, 0x88}, /* DRAM Driving – Group DQ (MD, MDQM) */ + {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */ + {0xe8, 0x88}, /* DRAM Driving – Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */ + {0xe6, 0xff}, /* DRAM Driving – Group DCLK0 (DCLK[2:0] for DIMM0) */ + {0xe7, 0xff}, /* DRAM Driving – Group DCLK1 (DCLK[5:3] for DIMM1) */ + {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */ + {0x91, 0x08}, /* MCLKO Output Phase Delay - I */ + {0x92, 0x08}, /* MCLKO Output Phase Delay - II */ + {0x93, 0x16}, /* CS/CKE Output Phase Delay */ + {0x95, 0x16}, /* SCMD/MA Output Phase Delay */ + {0x9b, 0x3f}, /* Memory Clock Output Enable */ +}; + +static void vx900_dram_set_ma_map(u16 map) +{ + pci_write_config16(MCU, 0x52, map); +} + +static void vx900_dram_map_pins(u8 ba0, u8 ba1, u8 ba2, u8 ra0, u8 ra1) +{ + u16 map = 0; + + printram("Mapping address pins to DRAM pins:\n"); + printram(" BA0 -> A%u\n", ba0); + printram(" BA1 -> A%u\n", ba1); + printram(" BA2 -> A%u\n", ba2); + printram(" RA0 -> A%u\n", ra0); + printram(" RA1 -> A%u\n", ra1); + /* Make sure BA2 is enabled */ + map |= (1 << 11); + + /* + * Find RA1 (15:14) + * 00: A14 + * 01: A16 + * 10: A18 + * 11: A20 + */ + if ((ra1 & 0x01) || (ra1 < 14) || (ra1 > 20)) { + printram("Illegal mapping RA1 -> A%u\n", ra1); + return; + } + map |= (((ra1 - 14) >> 1) & 0x03) << 14; + + /* + * Find RA0 (13:12) + * 00: A15 + * 01: A17 + * 10: A19 + * 11: A21 + */ + if ((!(ra0 & 0x01)) || (ra0 < 15) || (ra0 > 21)) { + printram("Illegal mapping RA0 -> A%u\n", ra0); + return; + } + map |= (((ra0 - 15) >> 1) & 0x03) << 12; + + /* + * Find BA2 (10:8) + * x00: A14 + * x01: A15 + * x10: A18 + * x11: A19 + */ + switch (ba2) { + case 14: + map |= (0 << 8); + break; + case 15: + map |= (1 << 8); + break; + case 18: + map |= (2 << 8); + break; + case 19: + map |= (3 << 8); + break; + default: + printram("Illegal mapping BA2 -> A%u\n", ba2); + break; + } + + /* + * Find BA1 (6:4) + * 000: A12 + * 001: A14 + * 010: A16 + * 011: A18 + * 1xx: A20 + */ + if (((ba1 & 0x01)) || (ba1 < 12) || (ba1 > 20)) { + printram("Illegal mapping BA1 -> A%u\n", ba1); + return; + } + map |= (((ba1 - 12) >> 1) & 0x07) << 4; + + /* + * Find BA0 (2:0) + * 000: A11 + * 001: A13 + * 010: A15 + * 011: A17 + * 1xx: A19 + */ + if ((!(ba0 & 0x01)) || (ba0 < 11) || (ba0 > 19)) { + printram("Illegal mapping BA0 -> A%u\n", ba0); + return; + } + map |= (((ba0 - 11) >> 1) & 0x07) << 0; + + vx900_dram_set_ma_map(map); + +} + +static void vx900_dram_write_init_config(void) +{ + /* Keep our RAM space free of legacy stuff */ + vx900_disable_legacy_rom_shadow(); + + /* Now worry about the real RAM init */ + size_t i; + for (i = 0; i < (sizeof(mcu_init_config) / sizeof(pci_reg8)); i++) { + pci_write_config8(MCU, mcu_init_config[i].addr, + mcu_init_config[i].val); + } + vx900_dram_set_ma_map(VX900_CALIB_MA_MAP); + + /* FIXME: Slowing stuff down. Does this really help? */ + + //Fast cycle control for CPU-to-DRAM Read Cycle 0:Disabled. This CPU bus controller will wait for all data + pci_mod_config8(HOST_BUS, 0x51, (1 << 7), 0); + //Memory to CPU bus Controller Conversion Mode 1: Synchronous mode + pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 1)); +} + +static void dram_find_spds_ddr3(const dimm_layout * addr, dimm_info * dimm) +{ + size_t i = 0; + int dimms = 0; + do { + spd_raw_data spd; + spd_read(addr->spd_addr[i], spd); + spd_decode_ddr3(&dimm->dimm[i], spd); + if (dimm->dimm[i].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) + continue; + dimms++; + dram_print_spd_ddr3(&dimm->dimm[i]); + } while (addr->spd_addr[++i] != SPD_END_LIST + && i < VX900_MAX_DIMM_SLOTS); + + if (!dimms) + die("No DIMMs were found"); +} + +static void dram_find_common_params(const dimm_info * dimms, + ramctr_timing * ctrl) +{ + size_t i, valid_dimms; + memset(ctrl, 0, sizeof(ramctr_timing)); + ctrl->cas_supported = 0xff; + valid_dimms = 0; + for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { + const dimm_attr *dimm = &dimms->dimm[i]; + if (dimm->dram_type == SPD_MEMORY_TYPE_UNDEFINED) + continue; + valid_dimms++; + + if (valid_dimms == 1) { + /* First DIMM defines the type of DIMM */ + ctrl->dram_type = dimm->dram_type; + } else { + /* Check if we have mismatched DIMMs */ + if (ctrl->dram_type != dimm->dram_type) + die("Mismatched DIMM Types"); + } + /* Find all possible CAS combinations */ + ctrl->cas_supported &= dimm->cas_supported; + + /* Find the smallest common latencies supported by all DIMMs */ + ctrl->tCK = max(ctrl->tCK, dimm->tCK); + ctrl->tAA = max(ctrl->tAA, dimm->tAA); + ctrl->tWR = max(ctrl->tWR, dimm->tWR); + ctrl->tRCD = max(ctrl->tRCD, dimm->tRCD); + ctrl->tRRD = max(ctrl->tRRD, dimm->tRRD); + ctrl->tRP = max(ctrl->tRP, dimm->tRP); + ctrl->tRAS = max(ctrl->tRAS, dimm->tRAS); + ctrl->tRC = max(ctrl->tRC, dimm->tRC); + ctrl->tRFC = max(ctrl->tRFC, dimm->tRFC); + ctrl->tWTR = max(ctrl->tWTR, dimm->tWTR); + ctrl->tRTP = max(ctrl->tRTP, dimm->tRTP); + ctrl->tFAW = max(ctrl->tFAW, dimm->tFAW); + + } + + ctrl->n_dimms = valid_dimms; + if (!ctrl->cas_supported) + die("Unsupported DIMM combination. " + "DIMMS do not support common CAS latency"); + if (!valid_dimms) + die("No valid DIMMs found"); +} + +static void vx900_dram_phys_bank_range(const dimm_info * dimms, + rank_layout * ranks) +{ + size_t i; + for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { + if (dimms->dimm[i].dram_type == SPD_MEMORY_TYPE_UNDEFINED) + continue; + u8 nranks = dimms->dimm[i].ranks; + /* Make sure we save the flags */ + ranks->flags[i * 2 + 1] = ranks->flags[i * 2] = + dimms->dimm[i].flags; + /* Only Rank1 has a mirrored pin mapping */ + ranks->flags[i * 2].pins_mirrored = 0; + if (nranks > 2) + die("Found DIMM with more than two ranks, which is not " + "supported by this chipset"); + u32 size = dimms->dimm[i].size_mb; + if (nranks == 2) { + /* Each rank holds half the capacity of the DIMM */ + size >>= 1; + ranks->phys_rank_size_mb[i << 1] = size; + ranks->phys_rank_size_mb[(i << 1) | 1] = size; + } else { + /* Otherwise, everything is held in the first bank */ + ranks->phys_rank_size_mb[i << 1] = size; + ranks->phys_rank_size_mb[(i << 1) | 1] = 0;; + } + } +} + +#define Rank0_ODT 0 +#define Rank1_ODT 1 +#define Rank2_ODT 2 +#define Rank3_ODT 3 +/* + * This is the table that tells us which ODT pin to map to which rank. + * + * This table is taken from code provided by VIA, but no explanation was + * provided as to why it is done this way. It may be possible that this table is + * not suitable for the way we map ranks later on. + */ +static const u8 odt_lookup_table[][2] = { + /* RankMAP Rank 3 Rank 2 Rank 1 Rank 0 */ + { 0x01, (Rank3_ODT << 6) | (Rank2_ODT << 4) | (Rank1_ODT << 2) | Rank0_ODT}, + { 0x03, (Rank3_ODT << 6) | (Rank2_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT}, + { 0x04, (Rank3_ODT << 6) | (Rank2_ODT << 4) | (Rank1_ODT << 2) | Rank0_ODT}, + { 0x05, (Rank3_ODT << 6) | (Rank0_ODT << 4) | (Rank1_ODT << 2) | Rank2_ODT}, + { 0x07, (Rank3_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT}, + { 0x0c, (Rank2_ODT << 6) | (Rank3_ODT << 4) | (Rank1_ODT << 2) | Rank0_ODT}, + { 0x0d, (Rank0_ODT << 6) | (Rank0_ODT << 4) | (Rank1_ODT << 2) | Rank2_ODT}, + { 0x0f, (Rank0_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT}, + { 0, 0}, +}; + +static void vx900_dram_driving_ctrl(const dimm_info * dimm) +{ + size_t i, ndimms; + u8 val, rank_mask; + + rank_mask = 0; + /* For ODT range selection, datasheet recommends + * when 1 DIMM present: 60 Ohm + * when 2 DIMMs present: 120 Ohm */ + ndimms = 0; + for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { + if (dimm->dimm[i].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) + continue; + ndimms++; + rank_mask |= (1 << (i * 2)); + if (dimm->dimm[i].ranks > 1) + rank_mask |= (2 << (i * 2)); + } + val = (ndimms > 1) ? 0x0 : 0x1; + pci_write_config8(MCU, 0xd5, val << 2); + + /* DRAM ODT Lookup Table */ + for (i = 0; ; i++) + { + if (odt_lookup_table[i][0] == 0) { + printram("No ODT entry for rank mask %x\n", rank_mask); + die("Aborting"); + } + if (odt_lookup_table[i][0] != rank_mask) + continue; + + val = odt_lookup_table[i][1]; + break; + } + + printram("Mapping rank mask %x to ODT entry %.2x\n", rank_mask, val); + pci_write_config8(MCU, 0x9c, val); + + + for (i = 0; i < (sizeof(mcu_drv_ctrl_config) / sizeof(pci_reg8)); i++) { + pci_write_config8(MCU, mcu_drv_ctrl_config[i].addr, + mcu_drv_ctrl_config[i].val); + } +} + +static void vx900_pr_map_all_vr3(void) +{ + /* Enable all ranks and set them to VR3 */ + pci_write_config16(MCU, 0x54, 0xbbbb); +} + +/* Map physical rank pr to virtual rank vr */ +static void vx900_map_pr_vr(u8 pr, u8 vr) +{ + pr &= 0x3; + vr &= 0x3; + /* Enable rank (bit [3], and set the VR number bits [1:0] */ + u16 val = 0x8 | vr; + /* Now move the value to the appropriate PR */ + val <<= (pr * 4); + pci_mod_config16(MCU, 0x54, 0xf << (pr * 4), val); + printram("Mapping PR %u to VR %u\n", pr, vr); +} + +static u8 vx900_get_CWL(u8 CAS) +{ + /* Get CWL based on CAS using the following rule: + * _________________________________________ + * CAS: | 4T | 5T | 6T | 7T | 8T | 9T | 10T | 11T | + * CWL: | 5T | 5T | 5T | 6T | 6T | 7T | 7T | 8T | + */ + static const u8 cas_cwl_map[] = { 5, 5, 5, 6, 6, 7, 7, 8 }; + if (CAS > 11) + return 8; + return cas_cwl_map[CAS - 4]; +} + +static void vx900_dram_timing(ramctr_timing * ctrl) +{ + /* Here we are calculating latencies, and writing them to the appropiate + * registers. Some registers do not take latencies from 0T, for example: + * CAS: 000 = 4T, 001 = 5T, 010 = 6T, etc + * In this example we subtract 4T from the result for CAS: (val - 4) + * The & 0x07 after (val - T0) just makes sure that, no matter what + * crazy thing may happen, we do not write outside the bits allocated + * in the register */ + u8 reg8, val, tFAW, tRRD; + u32 val32; + + /* Maximum supported DDR3 frequency is 533MHz (DDR3 1066) + * so make sure we cap it if we have faster DIMMs */ + if (ctrl->tCK < TCK_533MHZ) + ctrl->tCK = TCK_533MHZ; + val32 = (1000 << 8) / ctrl->tCK; + printram("Selected DRAM frequency: %u MHz\n", val32); + + /* Now find the right DRAM frequency setting, + * and align it to the closest JEDEC standard frequency */ + if (ctrl->tCK <= TCK_533MHZ) { + val = 0x07; + ctrl->tCK = TCK_533MHZ; + } else if (ctrl->tCK <= TCK_400MHZ) { + val = 0x06; + ctrl->tCK = TCK_400MHZ; + } else if (ctrl->tCK <= TCK_333MHZ) { + val = 0x05; + ctrl->tCK = TCK_333MHZ; + } else if (ctrl->tCK <= TCK_266MHZ) { + val = 0x04; + ctrl->tCK = TCK_266MHZ; + } + + /* Find CAS and CWL latencies */ + val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; + printram("Minimum CAS latency : %uT\n", val); + /* Find lowest supported CAS latency that satisfies the minimum value */ + while (!((ctrl->cas_supported >> (val - 4)) & 1) + && (ctrl->cas_supported >> (val - 4))) { + val++; + } + /* Is CAS supported */ + if (!(ctrl->cas_supported & (1 << (val - 4)))) + printram("CAS not supported\n"); + printram("Selected CAS latency : %uT\n", val); + ctrl->CAS = val; + ctrl->CWL = vx900_get_CWL(ctrl->CAS); + printram("Selected CWL latency : %uT\n", ctrl->CWL); + /* Write CAS and CWL */ + reg8 = (((ctrl->CWL - 4) & 0x07) << 4) | ((ctrl->CAS - 4) & 0x07); + pci_write_config8(MCU, 0xc0, reg8); + + /* Find tRCD */ + val = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; + printram("Selected tRCD : %uT\n", val); + reg8 = ((val - 4) & 0x7) << 4; + /* Find tRP */ + val = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; + printram("Selected tRP : %uT\n", val); + reg8 |= ((val - 4) & 0x7); + pci_write_config8(MCU, 0xc1, reg8); + + /* Find tRAS */ + val = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; + printram("Selected tRAS : %uT\n", val); + reg8 = ((val - 15) & 0x7) << 4; + /* Find tWR */ + ctrl->WR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; + printram("Selected tWR : %uT\n", ctrl->WR); + reg8 |= ((ctrl->WR - 4) & 0x7); + pci_write_config8(MCU, 0xc2, reg8); + + /* Find tFAW */ + tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; + printram("Selected tFAW : %uT\n", tFAW); + /* Find tRRD */ + tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; + printram("Selected tRRD : %uT\n", tRRD); + val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */ + reg8 = ((val - 0) & 0x7) << 4; + reg8 |= ((tRRD - 2) & 0x7); + pci_write_config8(MCU, 0xc3, reg8); + + /* Find tRTP */ + val = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; + printram("Selected tRTP : %uT\n", val); + reg8 = ((val & 0x3) << 4); + /* Find tWTR */ + val = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; + printram("Selected tWTR : %uT\n", val); + reg8 |= ((val - 2) & 0x7); + pci_mod_config8(MCU, 0xc4, 0x3f, reg8); + + /* DRAM Timing for All Ranks - VI + * [7:6] CKE Assertion Minimum Pulse Width + * We probably don't want to mess with this just yet. + * [5:0] Refresh-to-Active or Refresh-to-Refresh (tRFC) + * tRFC = (30 + 2 * [5:0])T + * Since we previously set RxC4[7] + */ + reg8 = pci_read_config8(MCU, 0xc5); + val = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; + printram("Minimum tRFC : %uT\n", val); + if (val < 30) { + val = 0; + } else { + val = (val - 30 + 1) / 2; + } + ; + printram("Selected tRFC : %uT\n", 30 + 2 * val); + reg8 |= (val & 0x3f); + pci_write_config8(MCU, 0xc5, reg8); + + /* Where does this go??? */ + val = (ctrl->tRC + ctrl->tCK - 1) / ctrl->tCK; + printram("Required tRC : %uT\n", val); +} + +static void vx900_dram_freq(ramctr_timing * ctrl) +{ + u8 val; + + /* Program the DRAM frequency */ + + /* Step 1 - Reset the PLL */ + pci_mod_config8(MCU, 0x90, 0x00, 0x0f); + /* Wait at least 10 ns; VIA code delays by 640us */ + udelay(640); + + /* Step 2 - Set target frequency */ + if (ctrl->tCK <= TCK_533MHZ) { + val = 0x07; + ctrl->tCK = TCK_533MHZ; + } else if (ctrl->tCK <= TCK_400MHZ) { + val = 0x06; + ctrl->tCK = TCK_400MHZ; + } else if (ctrl->tCK <= TCK_333MHZ) { + val = 0x05; + ctrl->tCK = TCK_333MHZ; + } else { /*ctrl->tCK <= TCK_266MHZ */ + val = 0x04; + ctrl->tCK = TCK_266MHZ; + } + /* Restart the PLL with the desired frequency */ + pci_mod_config8(MCU, 0x90, 0x0f, val); + + /* Step 3 - Wait for PLL to stabilize */ + udelay(2000); + + /* Step 4 - Reset the DLL - Clear [7,4] */ + pci_mod_config8(MCU, 0x6b, 0x90, 0x00); + udelay(2000); + + /* Step 5 - Enable the DLL - Set bits [7,4] to 01b */ + pci_mod_config8(MCU, 0x6b, 0x00, 0x10); + udelay(2000); + + /* Step 6 - Start DLL Calibration - Set bit [7] */ + pci_mod_config8(MCU, 0x6b, 0x00, 0x80); + udelay(5); + + /* Step 7 - Finish DLL Calibration - Clear bit [7] */ + pci_mod_config8(MCU, 0x6b, 0x80, 0x00); + + /* Step 8 - If we have registered DIMMs, we need to set bit[0] */ + if (dimm_is_registered(ctrl->dram_type)) { + printram("Enabling RDIMM support in memory controller\n"); + pci_mod_config8(MCU, 0x6c, 0x00, 0x01); + } +} + +static void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, + u8 ods, u8 rtt_wr, u8 srt, u8 asr) +{ + /* The VX900 can send the MRS commands directly through hardware + * It does the MR2->MR3->MR1->MR0->LongZQ dance */ + u16 reg16 = 0; + + printram("Using Hardware method for DRAM MRS commands.\n"); + + if (asr) + reg16 |= (1 << 8); + if (srt) + reg16 |= (1 << 9); + reg16 |= ((rtt_wr & 0x03) << 12); + if (ma_swap) + reg16 |= (1 << 1); + reg16 |= ((ods & 0x03) << 2); + reg16 |= ((rtt_nom & 0x7) << 4); + reg16 |= 1; /* This is the trigger bit */ + printram("Hw MRS set is 0x%4x\n", reg16); + pci_write_config16(MCU, 0xcc, reg16); + /* Wait for MRS commands to be sent */ + while (pci_read_config8(MCU, 0xcc) & 1) ; +} + +#include "ddr3_mrs_util.h" +#include "ddr3_mrs_util.c" + +static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, + enum ddr3_mr1_ods ods, + enum ddr3_mr2_rttwr rtt_wr, + enum ddr3_mr2_srt_range srt, + enum ddr3_mr2_asr asr) +{ + mrs_cmd_t mrs; + u8 reg8, cas, cwl, twr; + + printram("Using Software method for DRAM MRS commands.\n"); + + /* Get CAS, CWL, and tWR that we programmed earlier */ + reg8 = pci_read_config8(MCU, 0xc0); + cas = (reg8 & 0x07) + 4; + cwl = ((reg8 >> 4) & 0x07) + 4; + reg8 = pci_read_config8(MCU, 0xc2); + twr = (reg8 & 0x07) + 4; + + /* Step 06 - Set Fun3_RX6B[2:0] to 001b (NOP Command Enable). */ + /* Was already done for us before calling us */ + + /* Step 07 - Read a double word from any address of the DIMM. */ + /* Was already done for us before calling us */ + + /* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */ + + /* Step 09 – Issue MR2 cycle. Read a double word from the address + * depended on DRAM’s Rtt_WR and CWL settings. */ + mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl); + if (ma_swap) + mrs = ddr3_mrs_swap_pins(mrs); + volatile_read(vx900_get_mrs_addr(mrs)); + + /* Step 10 – Issue MR3 cycle. Read a double word from the address 60000h + * to set DRAM to normal operation mode. */ + mrs = ddr3_get_mr3(0); + if (ma_swap) + mrs = ddr3_mrs_swap_pins(mrs); + volatile_read(vx900_get_mrs_addr(mrs)); + + /* Step 11 –Issue MR1 cycle. Read a double word from the address + * depended on DRAM’s output driver impedance and Rtt_Nom settings. + * The DLL enable field, TDQS field, write leveling enable field, + * additive latency field and Qoff field should be set to 0. */ + mrs = ddr3_get_mr1(DDR3_MR1_QOFF_ENABLE, DDR3_MR1_TQDS_DISABLE, rtt_nom, + DDR3_MR1_WRLVL_DISABLE, ods, DDR3_MR1_AL_DISABLE, + DDR3_MR1_DLL_ENABLE); + if (ma_swap) + mrs = ddr3_mrs_swap_pins(mrs); + volatile_read(vx900_get_mrs_addr(mrs)); + + /* Step 12 - Issue MR0 cycle. Read a double word from the address + * depended on DRAM’s burst length, CAS latency and write recovery time + * settings. + * The read burst type field should be set to interleave. + * The mode field should be set to normal mode. + * The DLL reset field should be set to No. + * The DLL control for precharge PD field should be set to Fast exit. + */ + mrs = ddr3_get_mr0(DDR3_MR0_PRECHARGE_FAST, twr, + DDR3_MR0_DLL_RESET_NO, DDR3_MR0_MODE_NORMAL, cas, + DDR3_MR0_BURST_TYPE_INTERLEAVED, + DDR3_MR0_BURST_LENGTH_CHOP); + volatile_read(vx900_get_mrs_addr(mrs)); + + /* Step 13 - Set Fun3_RX6B[2:0] to 110b (Long ZQ calibration cmd) */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x06); /* Long ZQ */ + /* Step 14 - Read a double word from any address of the DIMM. */ + volatile_read(0); + udelay(1000); +} + +static void vx900_dram_send_soft_mrs(mrs_cmd_t cmd, u8 pin_swap) +{ + u32 addr; + /* Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ + pci_mod_config8(MCU, 0x6b, 0x07, (3 << 0)); + /* Is this a funky rank with Address pins swapped? */ + if (pin_swap) + cmd = ddr3_mrs_swap_pins(cmd); + /* Find the address corresponding to the MRS */ + addr = vx900_get_mrs_addr(cmd); + /* Execute the MRS */ + volatile_read(addr); + /* Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x00); +} + +static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl, + const rank_layout * ranks) +{ + size_t i; + u8 rtt_nom, rtt_wr, ods, pinswap; + + /* Set BA[0/1/2] to [A17/18/19] */ + vx900_dram_set_ma_map(VX900_MRS_MA_MAP); + + /* Step 01 - Set Fun3_Rx6E[5] to 1b to support burst length. */ + pci_mod_config8(MCU, 0x6e, 0, 1 << 5); + /* Step 02 - Set Fun3_RX69[0] to 0b (Disable Multiple Page Mode). */ + pci_mod_config8(MCU, 0x69, (1 << 0), 0x00); + /* And set [7:6] to 10b ? */ + pci_write_config8(MCU, 0x69, 0x87); + + /* Step 03 - Set the target physical rank to virtual rank0 and other + * ranks to virtual rank3. */ + vx900_pr_map_all_vr3(); + + /* Step 04 - Set Fun3_Rx50 to D8h. */ + pci_write_config8(MCU, 0x50, 0xd8); + /* Step 05 - Set Fun3_RX6B[5] to 1b to de-assert RESET# and wait for at + * least 500 us. */ + pci_mod_config8(MCU, 0x6b, 0x00, (1 << 5)); + udelay(500); + + /* Step 6 -> 15 - Set the target physical rank to virtual rank 0 and + * other ranks to virtual rank 3. + * Repeat Step 6 to 14 for every rank present, then jump to Step 16. */ + for (i = 0; i < VX900_MAX_MEM_RANKS; i++) { + if (ranks->phys_rank_size_mb[i] == 0) + continue; + printram("Initializing rank %lu\n", i); + + /* Set target physical rank to virtual rank 0 + * other ranks to virtual rank 3*/ + vx900_map_pr_vr(i, 0); + + /* FIXME: Is this needed on HW init? */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x01); /* Enable NOP */ + volatile_read(0x0); /* Do NOP */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */ + + /* See init_dram_by_rank.c and get_basic_information.c + * in the VIA provided code */ + if (ctrl->n_dimms == 1) { + rtt_nom = DDR3_MR1_RTT_NOM_RZQ2; + rtt_wr = DDR3_MR2_RTTWR_OFF; + } else { + rtt_nom = DDR3_MR1_RTT_NOM_RZQ8; + rtt_wr = DDR3_MR2_RTTWR_RZQ2; + } + ods = ranks->flags[i].rzq7_supported ? + DDR3_MR1_ODS_RZQ7 : DDR3_MR1_ODS_RZQ6; + + pinswap = (ranks->flags[i].pins_mirrored); + if (pinswap) + printram("Pins mirrored\n"); + printram(" Swap : %x\n", pinswap); + printram(" rtt_nom : %x\n", rtt_nom); + printram(" ods : %x\n", ods); + printram(" rtt_wr : %x\n", rtt_wr); + if (0) + vx900_dram_ddr3_do_hw_mrs(pinswap, rtt_nom, ods, rtt_wr, 0, 0); + else + vx900_dram_ddr3_do_sw_mrs(pinswap, rtt_nom, ods, rtt_wr, 0, 0); + + /* Normal SDRAM Mode */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x00); + + /* Step 15, set the rank to virtual rank 3 */ + vx900_map_pr_vr(i, 3); + } + + /* Step 16 – Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x00); + + /* Set BA[0/1/2] to [A13/14/15] */ + vx900_dram_set_ma_map(VX900_CALIB_MA_MAP); + + /* Step 17 – Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */ + pci_mod_config8(MCU, 0x69, 0x00, (1 << 0)); + + printram("DIMM initialization sequence complete\n"); +} + +static void vx900_dram_enter_read_leveling(u8 pinswap) +{ + /* Precharge all before issuing read leveling MRS to DRAM */ + pci_mod_config8(MCU, 0x06b, 0x07, 0x02); + volatile_read(0x0); + udelay(1000); + + /* Enable read leveling: Set D0F3Rx71[7]=1 */ + pci_mod_config8(MCU, 0x71, 0, (1 << 7)); + + /* Put DRAM in read leveling mode */ + mrs_cmd_t cmd = ddr3_get_mr3(1); + vx900_dram_send_soft_mrs(cmd, pinswap); +} + +static void vx900_dram_exit_read_leveling(u8 pinswap) +{ + /* Disable read leveling, and put dram in normal operation mode */ + mrs_cmd_t cmd = ddr3_get_mr3(0); + vx900_dram_send_soft_mrs(cmd, pinswap); + + /* Disable read leveling: Set D0F3Rx71[7]=0 */ + pci_mod_config8(MCU, 0x71, (1 << 7), 0); +} + +/* We need to see if the window (difference between minimum and maximum) is + * large enough so that we actually have a valid window. The signal should be + * valid for at least 1T in general. If the window is significantly smaller, + * then chances are our widow does not latch at the correct time, and the + * calibration will not work */ +#define DQSI_THRESHOLD 0x10 +#define DQO_THRESHOLD 0x09 +#define DQSO_THRESHOLD 0x12 +#define DELAY_RANGE_GOOD 0 +#define DELAY_RANGE_BAD -1 +static u8 vx900_dram_check_calib_range(const delay_range * dly, u8 window) +{ + size_t i; + for (i = 0; i < 8; i++) { + if (dly->high[i] - dly->low[i] < window) + return DELAY_RANGE_BAD; + /* When our maximum value is lower than our min, both values + * have overshot, and the window is definitely invalid */ + if (dly->high[i] < dly->low[i]) + return DELAY_RANGE_BAD; + } + return DELAY_RANGE_GOOD; +} + +static void vx900_dram_find_avg_delays(vx900_delay_calib * delays) +{ + size_t i; + /* At this point, we have transmit delays for both DIMMA and DIMMB, each + * with a slightly different window We want to find the intersection of + * those windows, so that we have a constrained window which both + * DIMMA and DIMMB can use. The center of our constrained window will + * also be the safest setting for the transmit delays + * + * DIMMA window t:|xxxxxxxxxxxxxx---------------xxxxxxxxxxxxxxxxxxxxxxx| + * DIMMB window t:|xxxxxxxxxxxxxxxxxxx---------------xxxxxxxxxxxxxxxxxx| + * Safe window t:|xxxxxxxxxxxxxxxxxxx----------xxxxxxxxxxxxxxxxxxxxxxx| + */ + delay_range *tx_dq_a = &(delays->tx_dq[0]); + delay_range *tx_dq_b = &(delays->tx_dq[1]); + delay_range *tx_dqs_a = &(delays->tx_dqs[0]); + delay_range *tx_dqs_b = &(delays->tx_dqs[1]); + if (1) + for (i = 0; i < 8; i++) { + u8 dq_low = max(tx_dq_a->low[i], tx_dq_b->low[i]); + u8 dq_high = min(tx_dq_a->high[i], tx_dq_b->high[i]); + u8 dqs_low = max(tx_dqs_a->low[i], tx_dqs_b->low[i]); + u8 dqs_high = min(tx_dqs_a->high[i], tx_dqs_b->high[i]); + + /* Store our values in the first delay + * We cast to u16 to prevent overflows due to the + * addition */ + delays->tx_dq[0].avg[i] = + (u8) (((u16) dq_low + dq_high) / 2); + delays->tx_dqs[0].avg[i] = + (u8) (((u16) dqs_low + dqs_high) / 2); + } + + for (i = 0; i < 8; i++) { + u8 dq_avg = + (u8) (((u16) tx_dq_a->avg[i] + tx_dq_b->avg[i]) / 2); + u8 dqs_avg = + (u8) (((u16) tx_dqs_a->avg[i] + tx_dqs_b->avg[i]) / 2); + delays->tx_dq[0].avg[i] = dq_avg; + delays->tx_dqs[0].avg[i] = dqs_avg; + } +} + +static void vx900_rx_capture_range_calib(u8 pinswap) +{ + u8 reg8; + const u32 cal_addr = 0x20; + + /* Set IO calibration address */ + pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); + /* Data pattern must be 0x00 for this calibration + * See paragraph describing Rx8e */ + pci_write_config8(MCU, 0x8e, 0x00); + + /* Need to put DRAM and MCU in read leveling */ + vx900_dram_enter_read_leveling(pinswap); + + /* Data pattern must be 0x00 for this calibration + * See paragraph describing Rx8e */ + pci_write_config8(MCU, 0x8e, 0x00); + /* Trigger calibration */ + reg8 = 0xa0; + pci_write_config8(MCU, 0x71, reg8); + + /* Wait for it */ + while (pci_read_config8(MCU, 0x71) & 0x10) ; + vx900_dram_exit_read_leveling(pinswap); +} + +static void vx900_rx_dqs_delay_calib(u8 pinswap) +{ + const u32 cal_addr = 0x30; + + /* We need to disable refresh commands so that they don't interfere */ + const u8 ref_cnt = pci_read_config8(MCU, 0xc7); + pci_write_config8(MCU, 0xc7, 0); + /* Set IO calibration address */ + pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); + /* Data pattern must be 0x00 for this calibration + * See paragraph describing Rx8e */ + pci_write_config8(MCU, 0x8e, 0x00); + + /* Need to put DRAM and MCU in read leveling */ + vx900_dram_enter_read_leveling(pinswap); + + /* From VIA code; Undocumented + * In theory this enables MODT[3:0] to be asserted */ + pci_mod_config8(MCU, 0x9e, 0, 0x80); + + /* Trigger calibration: Set D0F3Rx71[1:0]=10b */ + pci_mod_config8(MCU, 0x71, 0x03, 0x02); + + /* Wait for calibration to complete */ + while (pci_read_config8(MCU, 0x71) & 0x02) ; + vx900_dram_exit_read_leveling(pinswap); + + /* Restore the refresh counter */ + pci_write_config8(MCU, 0xc7, ref_cnt); + + /* FIXME: should we save it before, or should we just set it as is */ + vx900_dram_set_ma_map(VX900_CALIB_MA_MAP); +} + +static void vx900_tx_dqs_trigger_calib(u8 pattern) +{ + /* Data pattern for calibration */ + pci_write_config8(MCU, 0x8e, pattern); + /* Trigger calibration */ + pci_mod_config8(MCU, 0x75, 0, 0x20); + /* Wait for calibration */ + while (pci_read_config8(MCU, 0x75) & 0x20) ; +} + +static void vx900_tx_dqs_delay_calib(void) +{ + const u32 cal_addr = 0x00; + /* Set IO calibration address */ + pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); + /* Set circuit to use calibration results - Clear Rx75[0] */ + pci_mod_config8(MCU, 0x75, 0x01, 0); + /* Run calibration with first data pattern */ + vx900_tx_dqs_trigger_calib(0x5a); + /* Run again with different pattern */ + vx900_tx_dqs_trigger_calib(0xa5); +} + +static void vx900_tx_dq_delay_calib(void) +{ + /* Data pattern for calibration */ + pci_write_config8(MCU, 0x8e, 0x5a); + /* Trigger calibration */ + pci_mod_config8(MCU, 0x75, 0, 0x02); + /* Wait for calibration */ + while (pci_read_config8(MCU, 0x75) & 0x02) ; +} + +static void vx900_rxdqs_adjust(delay_range * dly) +{ + /* Adjust Rx DQS delay after calibration has been run. This is + * recommended by VIA, but no explanation was provided as to why */ + size_t i; + for (i = 0; i < 8; i++) { + if (dly->low[i] < 3) { + if (i == 2 || i == 4) + dly->low[i] += 4; + else + dly->avg[i] += 3; + + } + + if (dly->high[i] > 0x38) + dly->avg[i] -= 6; + else if (dly->high[i] > 0x30) + dly->avg[i] -= 4; + + if (dly->avg[i] > 0x20) + dly->avg[i] = 0x20; + } + + /* Put Rx DQS delay into manual mode (Set Rx[2,0] to 01) */ + pci_mod_config8(MCU, 0x71, 0x05, 0x01); + /* Now write the new settings */ + vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL); + vx900_write_0x78_0x7f(dly->avg); +} + +static void vx900_dram_calibrate_recieve_delays(vx900_delay_calib * delays, + u8 pinswap) +{ + size_t n_tries = 0; + delay_range *rx_dq_cr = &(delays->rx_dq_cr); + delay_range *rx_dqs = &(delays->rx_dqs); + /* We really should be able to finish this in a single pass, but it may + * in very rare circumstances not work the first time. We define a limit + * on the number of tries so that we have a way of warning the user */ + const size_t max_tries = 100; + for (;;) { + if (n_tries++ >= max_tries) { + die("Could not calibrate recieve delays. Giving up"); + } + u8 result; + /* Run calibrations */ + if (0) { + /* If we run this if(0) block, everything else may fail + * putting a huge delay after this block sometimes fixes + * the issue. + * I kept this code in because the long-term plan is to + * figure out how to get this calibration mechanism + * running */ + vx900_rx_capture_range_calib(pinswap); + vx900_read_delay_range(rx_dq_cr, CALIB_RxDQ_CR); + dump_delay_range(*rx_dq_cr); + + } else { + /*FIXME: Cheating with Rx CR setting\ + * We need to either use Rx CR calibration + * or set up a table for the calibration */ + u8 *override = &(rx_dq_cr->avg[0]); + override[0] = 0x28; + override[1] = 0x1c; + override[2] = 0x28; + override[3] = 0x28; + override[4] = 0x2c; + override[5] = 0x30; + override[6] = 0x30; + override[7] = 0x34; + printram("Bypassing RxCR 78-7f calibration with:\n"); + dump_delay(rx_dq_cr->avg); + } + /* We need to put the setting on manual mode */ + pci_mod_config8(MCU, 0x71, 0, 1 << 4); + vx900_delay_calib_mode_select(CALIB_RxDQ_CR, CALIB_MANUAL); + vx900_write_0x78_0x7f(rx_dq_cr->avg); + + /************* RxDQS *************/ + vx900_rx_dqs_delay_calib(pinswap); + vx900_read_delay_range(rx_dqs, CALIB_RxDQS); + vx900_rxdqs_adjust(rx_dqs); + + result = vx900_dram_check_calib_range(rx_dqs, DQSI_THRESHOLD); + if (result != DELAY_RANGE_GOOD) + continue; + + /* We're good to go. Switch to manual and write the manual + * setting */ + pci_mod_config8(MCU, 0x71, 0, 1 << 0); + vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL); + vx900_write_0x78_0x7f(rx_dqs->avg); + break; + } + if (n_tries > 1) + printram("Hmm, we had to try %lu times before our calibration " + "was good.\n", n_tries); +} + +static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, + delay_range * tx_dqs) +{ + /* Same timeout reasoning as in recieve delays */ + size_t n_tries = 0; + const size_t max_tries = 100; + for (;;) { + if (n_tries++ >= max_tries) { + die("Could not calibrate transmit delays. Giving up"); + } + u8 result; + /************* TxDQS *************/ + vx900_tx_dqs_delay_calib(); + vx900_read_delay_range(tx_dqs, CALIB_TxDQS); + + result = vx900_dram_check_calib_range(tx_dqs, DQSO_THRESHOLD); + if (result != DELAY_RANGE_GOOD) + continue; + + /************* TxDQ *************/ + /* FIXME: not sure if multiple page mode should be enabled here + * Vendor BIOS does it */ + pci_mod_config8(MCU, 0x69, 0, 0x01); + + vx900_tx_dq_delay_calib(); + vx900_read_delay_range(tx_dq, CALIB_TxDQ); + + result = vx900_dram_check_calib_range(tx_dq, DQO_THRESHOLD); + if (result != DELAY_RANGE_GOOD) + continue; + + /* At this point, our RAM should give correct read-backs for + * addresses under 64 MB. If it doesn't, it won't work */ + if (ram_check_noprint_nodie(1 << 20, 1 << 20)) { + /* No, our RAM is not working, try again */ + //continue; + } + /* Good. We should be able to use this DIMM */ + /* That's it. We're done */ + break; + } + if (n_tries > 1) + printram("Hmm, we had to try %lu times before our calibration " + "was good.\n", n_tries); +} + +static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl, + const rank_layout * ranks) +{ + size_t i; + u8 val; + u8 dimm; + vx900_delay_calib delay_cal; + memset(&delay_cal, 0, sizeof(delay_cal)); + printram("Starting delay calibration\n"); + + /**** Read delay control ****/ + /* MD Input Data Push Timing Control; + * use values recommended in datasheet + * Setting this too low causes the Rx window to move below the range we + * need it so we can capture it with Rx_78_7f + * This causes Rx calibrations to be too close to 0, and Tx + * calibrations will fail. + * Setting this too high causes the window to move above the range. + */ + if (ctrl->tCK <= TCK_533MHZ) + val = 2; + else if (ctrl->tCK <= TCK_333MHZ) + val = 1; + else + val = 0; + val++; /* FIXME: vendor BIOS sets this to 3 */ + pci_mod_config8(MCU, 0x74, (0x03 << 1), ((val & 0x03) << 1)); + + /* FIXME: The vendor BIOS increases the MD input delay - WHY ? */ + pci_mod_config8(MCU, 0xef, (3 << 4), 3 << 4); + + /**** Write delay control ****/ + /* FIXME: The vendor BIOS does this, but WHY? + * See check_special_registers in VIA provided code. This value seems + * to depend on the DRAM frequency. + */ + /* Early DQ/DQS for write cycles */ + pci_mod_config8(MCU, 0x76, (3 << 2), 2 << 2); + /* FIXME: The vendor BIOS does this - Output preamble ? */ + pci_write_config8(MCU, 0x77, 0x10); + + /* Set BA[0/1/2] to [A17/18/19] */ + vx900_dram_set_ma_map(VX900_MRS_MA_MAP); + /* Disable Multiple Page Mode - Set Rx69[0] to 0 */ + pci_mod_config8(MCU, 0x69, (1 << 0), 0x00); + + /* It's very important that we keep all ranks which are not calibrated + * mapped to VR3. Even if we disable them, if they are mapped to VR0 + * (the rank we use for calibrations), the calibrations may fail in + * unexpected ways. */ + vx900_pr_map_all_vr3(); + + /* We only really need to run the receive calibrations once. They are + * meant to account for signal travel differences in the internal paths + * of the MCU, so it doesn't really matter which rank we use for this. + * Differences between ranks will be accounted for in the transmit + * calibration. */ + for (i = 0; i < VX900_MAX_DIMM_SLOTS; i += 2) { + /* Do we have a valid DIMM? */ + if (ranks->phys_rank_size_mb[i] + + ranks->phys_rank_size_mb[i + 1] == 0) + continue; + /* Map the first rank of the DIMM to VR0 */ + vx900_map_pr_vr(2 * i, 0); + /* Only run on first rank, remember? */ + break; + } + vx900_dram_calibrate_recieve_delays(&delay_cal, + ranks->flags[i].pins_mirrored); + printram("RX DQS calibration results\n"); + dump_delay_range(delay_cal.rx_dqs); + + /* Enable multiple page mode for when calibrating transmit delays */ + pci_mod_config8(MCU, 0x69, 0, 1 << 1); + + /* Unlike the recieve delays, we need to run the transmit calibration + * for each DIMM (not rank) */ + dimm = 0; + for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { + /* Do we have a valid DIMM? */ + u32 dimm_size_mb = ranks->phys_rank_size_mb[2 * i] + + ranks->phys_rank_size_mb[2 * i + 1]; + if (dimm_size_mb == 0) + continue; + /* Map the first rank of the DIMM to VR0 */ + vx900_map_pr_vr(2 * i, 0); + vx900_dram_calibrate_transmit_delays(&(delay_cal.tx_dq[dimm]), + &(delay_cal.tx_dqs[dimm])); + /* We run this more than once, so dump delays for each DIMM */ + printram("Tx DQS calibration results\n"); + dump_delay_range(delay_cal.tx_dqs[dimm]); + printram("TX DQ delay calibration results:\n"); + dump_delay_range(delay_cal.tx_dq[dimm]); + /* Now move the DIMM back to VR3 */ + vx900_map_pr_vr(2 * i, 3); + /* We use dimm as a counter so that we fill tx_dq[] and tx_dqs[] + * results in order from 0, and do not leave any gaps */ + dimm++; + } + + /* When we have more dimms, we need to find a tx window with which all + * dimms can safely work */ + if (dimm > 1) { + vx900_dram_find_avg_delays(&delay_cal); + printram("Final delay values\n"); + printram("Tx DQS: "); + dump_delay(delay_cal.tx_dqs[0].avg); + printram("Tx DQ: "); + dump_delay(delay_cal.tx_dq[0].avg); + } + /* Write manual settings */ + pci_mod_config8(MCU, 0x75, 0, 0x01); + vx900_delay_calib_mode_select(CALIB_TxDQS, CALIB_MANUAL); + vx900_write_0x78_0x7f(delay_cal.tx_dqs[0].avg); + vx900_delay_calib_mode_select(CALIB_TxDQ, CALIB_MANUAL); + vx900_write_0x78_0x7f(delay_cal.tx_dq[0].avg); +} + +static void vx900_dram_set_refresh_counter(ramctr_timing * ctrl) +{ + u8 reg8; + /* Set DRAM refresh counter + * Based on a refresh counter of 0x61 at 400MHz */ + reg8 = (TCK_400MHZ * 0x61) / ctrl->tCK; + pci_write_config8(MCU, 0xc7, reg8); +} + +static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks) +{ + size_t i, vrank = 0; + u8 reg8; + u32 ramsize_mb = 0, tolm_mb; + const u32 TOLM_3_5G = (7 << 29); + /* All unused physical ranks go to VR3. Otherwise, the MCU might be + * trying to read or write from unused ranks, or even worse, write some + * bits to the rank we want, and some to the unused ranks, even though + * they are disabled. Since VR3 is the last virtual rank to be used, we + * eliminate any ambiguities that the MCU may face. */ + vx900_pr_map_all_vr3(); + for (i = 0; i < VX900_MAX_MEM_RANKS; i++) { + u32 rank_size_mb = ranks->phys_rank_size_mb[i]; + if (!rank_size_mb) + continue; + ranks->virt[vrank].start_addr = ramsize_mb; + ramsize_mb += rank_size_mb; + ranks->virt[vrank].end_addr = ramsize_mb; + + /* Rank memory range */ + reg8 = (ranks->virt[vrank].start_addr >> 6); + pci_write_config8(MCU, 0x48 + vrank, reg8); + reg8 = (ranks->virt[vrank].end_addr >> 6); + pci_write_config8(MCU, 0x40 + vrank, reg8); + + vx900_map_pr_vr(i, vrank); + + printram("Mapped Physical rank %u, to virtual rank %u\n" + " Start address: 0x%.10llx\n" + " End address: 0x%.10llx\n", + (int)i, (int)vrank, + (u64)ranks->virt[vrank].start_addr << 20, + (u64)ranks->virt[vrank].end_addr << 20); + /* Move on to next virtual rank */ + vrank++; + } + + /* Limit the Top of Low memory at 3.5G + * Not to worry, we'll set tolm in ramstage, once we have initialized + * all devices and know pci_tolm. */ + tolm_mb = ramsize_mb; + tolm_mb = min(tolm_mb, TOLM_3_5G >> 20); + u16 reg_tolm = (tolm_mb << 4) & 0xfff0; + pci_mod_config16(MCU, 0x84, 0xfff0, reg_tolm); + + printram("Initialized %u virtual ranks, with a total size of %u MB\n", + (int)vrank, ramsize_mb); +} + +static void vx900_dram_write_final_config(ramctr_timing * ctrl) +{ + + /* FIXME: These are quick cheats */ + pci_write_config8(MCU, 0x50, 0xa0); /* DRAM MA map */ + ///vx900_dram_set_ma_map(VX900_CALIB_MA_MAP); /* Rank interleave */ + vx900_dram_map_pins(13, 14, 15, 17, 16); + + //pci_write_config8(MCU, 0x69, 0xe7); + /* Enable paging mode and 8 page registers */ + pci_mod_config8(MCU, 0x69, 0, 0xe5); + //pci_write_config8(MCU, 0x72, 0x0f); + + //pci_write_config8(MCU, 0x97, 0xa4); /* self-refresh */ + //pci_write_config8(MCU, 0x98, 0xba); /* self-refresh II */ + //pci_write_config8(MCU, 0x9a, 0x80); /* self-refresh III */ + + /* Enable automatic triggering of short ZQ calibration */ + pci_write_config8(MCU, 0xc8, 0x80); +} + +void vx900_init_dram_ddr3(const dimm_layout * dimm_addr) +{ + dimm_info dimm_prop; + ramctr_timing ctrl_prop; + rank_layout ranks; + device_t mcu; + + if (!ram_check_noprint_nodie(1 << 20, 1 << 20)) { + printram("RAM is already initialized. Skipping init\n"); + return; + } + /* Locate the Memory controller */ + mcu = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL), 0); + + if (mcu == PCI_DEV_INVALID) { + die("Memory Controller not found\n"); + } + memset(&dimm_prop, 0, sizeof(dimm_prop)); + memset(&ctrl_prop, 0, sizeof(ctrl_prop)); + memset(&ranks, 0, sizeof(ranks)); + /* 1) Write some initial "safe" parameters */ + vx900_dram_write_init_config(); + /* 2) Get timing information from SPDs */ + dram_find_spds_ddr3(dimm_addr, &dimm_prop); + /* 3) Find lowest common denominator for all modules */ + dram_find_common_params(&dimm_prop, &ctrl_prop); + /* 4) Find the size of each memory rank */ + vx900_dram_phys_bank_range(&dimm_prop, &ranks); + /* 5) Set DRAM driving strength */ + vx900_dram_driving_ctrl(&dimm_prop); + /* 6) Set DRAM frequency and latencies */ + vx900_dram_timing(&ctrl_prop); + vx900_dram_freq(&ctrl_prop); + /* 7) Initialize the modules themselves */ + vx900_dram_ddr3_dimm_init(&ctrl_prop, &ranks); + /* 8) Set refresh counter based on DRAM frequency */ + vx900_dram_set_refresh_counter(&ctrl_prop); + /* 9) Calibrate receive and transmit delays */ + vx900_dram_calibrate_delays(&ctrl_prop, &ranks); + /* 10) Enable Physical to Virtual Rank mapping */ + vx900_dram_range(&ctrl_prop, &ranks); + /* 99) Some final adjustments */ + vx900_dram_write_final_config(&ctrl_prop); + /* Take a dump */ + dump_pci_device(mcu); + +} diff --git a/src/northbridge/via/vx900/romstrap.inc b/src/northbridge/via/vx900/romstrap.inc new file mode 100644 index 0000000..e4ce677 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.inc @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu yhlu@tyan.com for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * Copyright (C) 2011-2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* As extracted from the manufacturer's ROM, the romstrap table looks like: + * .long 0x77886047 .long 0x00777777 + * .long 0x00000000 .long 0x00000000 + * .long 0x00888888 .long 0x00AA1111 + * .long 0x00000000 .long 0x00000000 + * + * The vendor BIOS then adjusts some of these settings very early on. Instead of + * adjusting those settings in code, we work them in the romstrap table. + * + */ +/* This file constructs the ROM strap table for VX900 */ + + .section ".romstrap", "a", @progbits + + .globl __romstrap_start +__romstrap_start: +tblpointer: + .long 0x77886047 + .long 0x00777777 + .long 0x00000000 + .long 0x00000000 + .long 0x00888888 + .long 0x00AA1111 + .long 0x00000000 + .long 0x00000000 + +/* + * The pointer to above table should be at 0xffffffd0, + * the table itself MUST be aligned to 128B it seems! + */ +rspointers: + .long tblpointer // It will be 0xffffffd0 + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/northbridge/via/vx900/romstrap.lds b/src/northbridge/via/vx900/romstrap.lds new file mode 100644 index 0000000..fc63c05 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.lds @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu yinghai.lu@amd.com for AMD) + * Copyright (C) 2011 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/ + */ + +SECTIONS { + . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c new file mode 100644 index 0000000..d0b70ff --- /dev/null +++ b/src/northbridge/via/vx900/sata.c @@ -0,0 +1,295 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include "vx900.h" + +static void dump_pci_device(device_t dev) +{ + int i; + for (i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + if((i & 7) == 0) print_debug(" |"); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} + +static void vx900_print_sata_errors(u32 flags) +{ + /* Status flags */ + printk(BIOS_DEBUG, "\tPhyRdy %s\n", + (flags&(1<<16)) ? "changed" : "not changed"); + printk(BIOS_DEBUG, "\tCOMWAKE %s\n", + (flags&(1<<16)) ? "detected" : "not detected"); + printk(BIOS_DEBUG, "\tExchange as determined by COMINIT %s\n", + (flags&(1<<26)) ? "occured" : "not occured"); + printk(BIOS_DEBUG, "\tPort selector presence %s\n", + (flags&(1<<27)) ? "detected" : "not detected"); + /* Errors */ + if(flags&(1<<0)) + print_debug("\tRecovered data integrity ERROR\n"); + if(flags&(1<<1)) + print_debug("\tRecovered data communication ERROR\n"); + if(flags&(1<<8)) + print_debug("\tNon-recovered Transient Data Integrity ERROR\n"); + if(flags&(1<<9)) + print_debug("\tNon-recovered Persistent Communication or" + "\tData Integrity ERROR\n"); + if(flags&(1<<10)) + print_debug("\tProtocol ERROR\n"); + if(flags&(1<<11)) + print_debug("\tInternal ERROR\n"); + if(flags&(1<<17)) + print_debug("\tPHY Internal ERROR\n"); + if(flags&(1<<19)) + print_debug("\t10B to 8B Decode ERROR\n"); + if(flags&(1<<20)) + print_debug("\tDisparity ERROR\n"); + if(flags&(1<<21)) + print_debug("\tCRC ERROR\n"); + if(flags&(1<<22)) + print_debug("\tHandshake ERROR\n"); + if(flags&(1<<23)) + print_debug("\tLink Sequence ERROR\n"); + if(flags&(1<<24)) + print_debug("\tTransport State Transition ERROR\n"); + if(flags&(1<<25)) + print_debug("\tUNRECOGNIZED FIS type\n"); +} + +static void vx900_dbg_sata_errors(device_t dev) +{ + /* Port 0 */ + if (pci_read_config8(dev, 0xa0) & (1<<0) ) { + print_debug("Device detected in SATA port 0.\n"); + u32 flags = pci_read_config32(dev, 0xa8); + vx900_print_sata_errors(flags); + }; + /* Port 1 */ + if (pci_read_config8(dev, 0xa1) & (1<<0) ) { + print_debug("Device detected in SATA port 1.\n"); + u32 flags = pci_read_config32(dev, 0xac); + vx900_print_sata_errors(flags); + }; +} + +typedef u8 sata_phy_config[64]; + +static sata_phy_config reference_ephy = { + 0x80, 0xb8, 0xf0, 0xfe, 0x40, 0x7e, 0xf6, 0xdd, + 0x1a, 0x22, 0xa0, 0x10, 0x02, 0xa9, 0x7c, 0x7e, + 0x00, 0x00, 0x00, 0x00, 0x40, 0x30, 0x84, 0x8c, + 0x75, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x40, 0xd0, 0x41, 0x40, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x40, 0x50, 0x41, 0x40, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static u32 sata_phy_read32(device_t dev, u8 index) +{ + /* The SATA PHY control registers are accessed by a funny index/value + * scheme. Each byte (0,1,2,3) has its own 4-bit index */ + index = (index >> 2) & 0xf; + u16 i16 = index | (index<<4) | (index<<8)| (index<<12); + /* The index */ + pci_write_config16(dev, 0x68, i16); + /* The value */ + return pci_read_config32(dev, 0x64); +} + +static void sata_phy_write32(device_t dev, u8 index, u32 val) +{ + /* The SATA PHY control registers are accessed by a funny index/value + * scheme. Each byte (0,1,2,3) has its own 4-bit index */ + index = (index >> 2) & 0xf; + u16 i16 = index | (index<<4) | (index<<8)| (index<<12); + /* The index */ + pci_write_config16(dev, 0x68, i16); + /* The value */ + pci_write_config32(dev, 0x64, val); +} + +static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) +{ + size_t i; + u32* data = (u32*)cfg; + for(i = 0; i < (sizeof(sata_phy_config) ) >> 2; i++) { + data[i] = sata_phy_read32(dev, i<<2); + } +} + +static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg) +{ + size_t i; + u32* data = (u32*)cfg; + for(i = 0; i < (sizeof(sata_phy_config) ) >> 2; i++) { + sata_phy_write32(dev, i<<2, data[i]); + } +} + +static void vx900_sata_dump_phy_config(sata_phy_config cfg) +{ + print_debug("SATA PHY config:\n"); + int i; + for (i = 0; i < sizeof(sata_phy_config); i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = cfg[i]; + if((i & 7) == 0) print_debug(" |"); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} + +/** + * \brief VX900: Place the onboard SATA controller in Native IDE mode + * + * AHCI mode requires a sub-class of 0x06, and Interface of 0x0 + * SATA mode requires a sub-class of 0x06, and Interface of 0x00 + * Unfortunately, setting the class to SATA, will prevent us from modyfing the + * interface register to an AHCI/SATA compliant value. Thus, payloads or OS may + * not properly identify this as a SATA controller. + * We could set the class code to 0x04, which would cause the interface register + * to become 0x00, which represents a RAID controller. Unfortunately, when we do + * this, SeaBIOS will skip this as a storage device, and we will not be able to + * boot. + * Our only option is to operate in IDE mode. We choose native IDE so that we + * can freely assign an IRQ, and are not forced to use IRQ14 + */ +static void vx900_native_ide_mode(device_t dev) +{ + /* Disable subclass write protect */ + pci_mod_config8(dev, 0x45, 1<<7, 0); + /* Change the device class to IDE */ + pci_write_config16(dev, PCI_CLASS_DEVICE, PCI_CLASS_STORAGE_IDE); + /* Re-enable subclass write protect */ + pci_mod_config8(dev, 0x45, 0, 1<<7); + /* Put it in native IDE mode */ + pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); +} + +static void vx900_sata_init(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== SATA init \n"); + print_debug("======================================================\n"); + + /* Enable SATA primary channel IO access */ + pci_mod_config8(dev, 0x40, 0, 1<<1); + /* Just SATA, so it makes sense to be in native SATA mode */ + vx900_native_ide_mode(dev); + + /* TP Layer Idle at least 20us before the Following Command */ + pci_mod_config8(dev, 0x53, 0, 1<<7); + /* Resend COMRESET When Recovering SATA Gen2 Device Error */ + pci_mod_config8(dev, 0x62, 1<<1, 1<<7); + + /* Fix "PMP Device Can’t Detect HDD Normally" (VIA Porting Guide) + * SATA device detection will not work unless we clear these bits. + * Without doing this, SeaBIOS (and potentially other payloads) will + * timeout when detecting SATA devices */ + pci_mod_config8(dev, 0x89, (1<<3) | (1<<6), 0); + + /* 12.7 Two Software Resets May Affect the System + * When the software does the second reset before the first reset + * finishes, it may cause the system hang. It would do one software + * reset and check the BSY bit of one port only, and the BSY bit of + * other port would be 1, then it does another software reset + * immediately and causes the system hang. + * This is because the first software reset doesn’t finish, and the + * state machine of the host controller conflicts, it can’t finish the + * second one anymore. The BSY bit of slave port would be always 1 after + * the second software reset issues. BIOS should set the following + * bit to avoid this issue. */ + pci_mod_config8(dev, 0x80, 0, 1<<6); + + /* We need to set the EPHY values before doing anything with the link */ + sata_phy_config ephy; + vx900_sata_read_phy_config(dev, ephy); + if(1) { + vx900_sata_dump_phy_config(ephy); + vx900_sata_write_phy_config(dev, reference_ephy); + } else { + /* Enable TX and RX driving resistance */ + /* TX - 50 Ohm */ + ephy[1] &= ~(0x1f<<3); + ephy[1] |= (1<<7) | (8<<3); + /* RX - 50 Ohm */ + ephy[2] &= ~(0x1f<<3); + ephy[2] |= (1<<7) | (8<<3); + vx900_sata_write_phy_config(dev, ephy); + } + + vx900_sata_read_phy_config(dev, ephy); + vx900_sata_dump_phy_config(ephy); + + /* Clear error flags */ + pci_write_config32(dev, 0xa8, 0xffffffff); + pci_write_config32(dev, 0xac, 0xffffffff); + + /* Start OOB link negotiation sequence */ + pci_mod_config8(dev, 0xb9, 0, 3<<4); + + /* FIXME: From now on, we are just doing DEBUG stuff + * Wait until PHY communication is enabled */ + u32 wloops = 0; + while(! (pci_read_config8(dev, 0xa0) & (1<<1)) ) wloops ++; + printk(BIOS_SPEW, "wloops: %u\n", wloops); + + print_debug("And finally, the dump you've all been waiting for\n"); + dump_pci_device(dev); + vx900_dbg_sata_errors(dev); +} + +static void vx900_sata_read_resources(device_t dev) +{ + pci_dev_read_resources(dev); +} + +static struct device_operations vga_operations = { + .read_resources = vx900_sata_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vx900_sata_init, +}; + +static const struct pci_driver chrome9hd_driver __pci_driver = { + .ops = &vga_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_SATA, +}; \ No newline at end of file diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c new file mode 100644 index 0000000..f371854 --- /dev/null +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <drivers/generic/ioapic/chip.h> + +#include "vx900.h" +#include "chip.h" + +/** + * \brief VX900: Set up the north module IOAPIC (for PCIE and VGA) + * + * Enable the IOAPIC in the south module, and properly set it up. + * \n + * This is the hardware specific initialization for the IOAPIC, and complements + * the setup done by the generic IOAPIC driver. In order for the IOAPIC to work + * properly, it _must_ be declared in devicetree.cb . + * \n + * We are assuming this is called before the drivers/generic/ioapic code, + * which should be the case if devicetree.cb is set up properly. + */ +static void vx900_north_ioapic_setup(device_t dev) +{ + u8 base_val; + device_t ioapic; + ioapic_config_t *config; + /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb + * If it's not, then the generic ioapic driver will not set it up + * correctly, and the MP table will not be correctly generated */ + for(ioapic = dev->next; ioapic; ioapic = ioapic->next) + { + if(ioapic->path.type == DEVICE_PATH_IOAPIC) + break; + } + /* You did put an IOAPIC in devicetree.cb, didn't you? */ + if(ioapic == 0) { + /* We don't have enough info to set up the IOAPIC */ + printk(BIOS_ERR, "ERROR: North module IOAPIC not found. " + "Check your devicetree.cb\n"); + return; + } + /* Found our IOAPIC, and it should not carry ISA interrupts */ + config = (ioapic_config_t*)ioapic->chip_info; + if(config->have_isa_interrupts) { + /* Umh, is this the right IOAPIC ? */ + printk(BIOS_ERR, "ERROR: North module IOAPIC should not carry " + "ISA interrupts.\n" + "Check your devicetree.cb\n"); + printk(BIOS_ERR, "Will not initialize this IOAPIC.\n"); + return; + } + /* The base address of this IOAPIC _must_ + * be between 0xfec00000 and 0xfecfff00 + * be 256-byte aligned + */ + if( (config->base < 0xfec0000 || config->base > 0xfecfff00) + || (( config->base & 0xff ) != 0) ) + { + printk(BIOS_ERR, "ERROR: North module IOAPIC base should be " + "between 0xfec00000 and 0xfecfff00\n" + "and must be aligned to a 256-byte boundary, " + "but we found it at 0x%.8x\n", config->base); + return; + } + + printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC " + "at 0%.8x\n", config->base); + + /* First register of the IOAPIC base */ + base_val = (config->base >> 8) & 0xff; + pci_write_config8(dev, 0x41, base_val); + /* Second register of the base. + * Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */ + base_val = (config->base >> 16) & 0xf; + pci_mod_config8(dev, 0x40, 0, base_val | (1<<7) | (1<<5) ); +} + +/* + * Configures the PCI-express ports + * + * FIXME: implement this + */ +static void vx900_pex_link_setup(device_t dev) +{ + u8 reg8; + struct northbridge_via_vx900_config *nb = (void*)dev->chip_info; + + print_debug("======================================================\n"); + print_debug("== PEX link setup\n"); + print_debug("======================================================\n"); + + /* Check the default boot config */ + reg8 = pci_read_config8(dev, 0xb0); + if (reg8 && (1 << 7) ) + print_debug("PCIE lanes 3:0 used as DP interface\n"); + else + print_debug("PCIE lanes 3:0 used for Root Port 0\n"); + + if (reg8 && (1 << 3)) + print_debug("Root Port 0 is 1 lane wide\n"); + else + print_debug("Root Port 0 is 2 lanes wide\n"); + + reg8 &= ~( (1 << 7) | (1 << 3)); + + if (nb->assign_pex_to_dp) + reg8 |= (1 << 7); + + if (!nb->pcie_port1_2_lane_wide) + reg8 |= (1 << 3); + + pci_write_config8(dev, 0xb0, reg8); +} + +static void vx900_traf_ctr_init(device_t dev) +{ + vx900_north_ioapic_setup(dev); + vx900_pex_link_setup(dev); +} + + +static struct device_operations traf_ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vx900_traf_ctr_init, + /* Need this here, or the IOAPIC driver won't be called */ + .scan_bus = scan_static_bus, +}; + +static const struct pci_driver traf_ctrl_driver __pci_driver = { + .ops = &traf_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_TRAF, +}; \ No newline at end of file diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h new file mode 100644 index 0000000..001d10f --- /dev/null +++ b/src/northbridge/via/vx900/vx900.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ +#ifndef __VX900_H +#define __VX900_H + +#define VX900_ACPI_IO_BASE 0x0400 + +#define VX900_NB_IOAPIC_ID 0x2 +#define VX900_NB_IOAPIC_BASE 0xfecc000 + +#define VX900_SB_IOAPIC_ID 0x1 +#define VX900_SB_IOAPIC_BASE 0xfec0000 + +#define SMBUS_IO_BASE 0x500 + +/* The maximum number of DIMM slots that the VX900 supports */ +#define VX900_MAX_DIMM_SLOTS 2 +#define VX900_MAX_MEM_RANKS 4 + +#define min(a,b) a<b?a:b +#define max(a,b) a>b?a:b + +#include <arch/io.h> +#ifndef __PRE_RAM__ +#include <device/pci.h> +#else +//#include <arch/romcc_io.h> +#endif /* __PRE_RAM__ */ + + +/* We use these throughout the code. They really belong in a generic part of + * coreboot, but until beuraucracy gets them there, we still need them */ +static inline __attribute__((always_inline)) +void pci_mod_config8(device_t dev, unsigned int where, + uint8_t clr_mask, uint8_t set_mask) +{ + uint8_t reg8 = pci_read_config8(dev, where); + reg8 &= ~clr_mask; + reg8 |= set_mask; + pci_write_config8(dev, where, reg8); +} +static inline __attribute__((always_inline)) +void pci_mod_config16(device_t dev, unsigned int where, + uint16_t clr_mask, uint16_t set_mask) +{ + uint16_t reg16 = pci_read_config16(dev, where); + reg16 &= ~clr_mask; + reg16 |= set_mask; + pci_write_config16(dev, where, reg16); +} +static inline __attribute__((always_inline)) +void pci_mod_config32(device_t dev, unsigned int where, + uint32_t clr_mask, uint32_t set_mask) +{ + uint32_t reg32 = pci_read_config32(dev, where); + reg32 &= ~clr_mask; + reg32 |= set_mask; + pci_write_config32(dev, where, reg32); +} + +u32 chrome9hd_fb_size(void); +#endif /* __VX900_H */
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Alexandru Gagniuc