Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46978 )
Change subject: soc/intel/broadwell: Use common southbridge RCBA ......................................................................
soc/intel/broadwell: Use common southbridge RCBA
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I7f483423942dcdd317fb6b70c8f6200aaf548e80 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/acpi/hostbridge.asl M src/soc/intel/broadwell/memmap.h M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/rcba.h M src/southbridge/intel/lynxpoint/acpi/pch.asl 6 files changed, 6 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46978/1
diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 8b63ec7..5a08554 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/intel/broadwell/memmap.h> +#include <southbridge/intel/common/rcba.h>
Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI diff --git a/src/soc/intel/broadwell/memmap.h b/src/soc/intel/broadwell/memmap.h index e69b88e..0e6195c 100644 --- a/src/soc/intel/broadwell/memmap.h +++ b/src/soc/intel/broadwell/memmap.h @@ -13,8 +13,6 @@ #define GDXC_BASE_ADDRESS 0xfed84000 #define GDXC_BASE_SIZE 0x1000
-#define DEFAULT_RCBA 0xfed1c000 - #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000
diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index fa6ff95..3fe2568 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -14,7 +14,7 @@
static void map_rcba(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); }
static void enable_port80_on_lpc(void) @@ -49,7 +49,7 @@ static void pch_enable_bars(void) { /* Set up southbridge BARs */ - pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index d5ecdeb..550540d 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -499,9 +499,9 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* RCBA */ - if (default_decode_base > DEFAULT_RCBA) { + if (default_decode_base > (uintptr_t)DEFAULT_RCBA) { res = new_resource(dev, RCBA); - res->base = DEFAULT_RCBA; + res->base = (uintptr_t)DEFAULT_RCBA; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; diff --git a/src/soc/intel/broadwell/pch/rcba.h b/src/soc/intel/broadwell/pch/rcba.h index 7293dff..2649e9c 100644 --- a/src/soc/intel/broadwell/pch/rcba.h +++ b/src/soc/intel/broadwell/pch/rcba.h @@ -3,18 +3,7 @@ #ifndef _BROADWELL_RCBA_H_ #define _BROADWELL_RCBA_H_
-#include <soc/intel/broadwell/memmap.h> - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) +#include <southbridge/intel/common/rcba.h>
#define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a081c1f..d18832b 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -2,10 +2,6 @@
/* Intel Lynx Point PCH support */
-#if CONFIG(SOC_INTEL_BROADWELL) -#include <soc/intel/broadwell/memmap.h> -#endif - #if CONFIG(INTEL_LYNXPOINT_LP) #define DEFAULT_PRW_VALUE 0x6d #else
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46978
to look at the new patch set (#5).
Change subject: soc/intel/broadwell: Use common southbridge RCBA ......................................................................
soc/intel/broadwell: Use common southbridge RCBA
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I7f483423942dcdd317fb6b70c8f6200aaf548e80 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/acpi/hostbridge.asl M src/soc/intel/broadwell/memmap.h M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/rcba.h M src/southbridge/intel/lynxpoint/acpi/pch.asl 6 files changed, 6 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46978/5
-
Angel Pons (Code Review)