[M] Change in coreboot[main]: soc/mediatek/mt8196: Add SPI driver support

[Jarried Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu.

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84930?usp=email )

Change subject: soc/mediatek/mt8196: Add SPI driver support
......................................................................

soc/mediatek/mt8196: Add SPI driver support

Add SPI controlleer driver code.

Test=Build pass
BUG=b:317009620

Change-Id: I10dd1105931c4911ce5257803073b7af76115c75
Signed-off-by: Liya Li 
---
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/include/soc/spi.h
M src/soc/mediatek/mt8196/spi.c
3 files changed, 122 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84930/1

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 7df8e8a..53d9b35 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -7,7 +7,7 @@
 all-y += ../common/i2c.c i2c.c
 all-y += mtcmos.c
 all-y += ../common/pll.c pll.c
-all-$(CONFIG_SPI_FLASH) += spi.c
+all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += timer.c timer_prepare.c
 all-y += ../common/uart.c

diff --git a/src/soc/mediatek/mt8196/include/soc/spi.h b/src/soc/mediatek/mt8196/include/soc/spi.h
index 43edc89..4722ae5 100644
--- a/src/soc/mediatek/mt8196/include/soc/spi.h
+++ b/src/soc/mediatek/mt8196/include/soc/spi.h
@@ -5,10 +5,24 @@
  * Chapter number: 13.9
  */

-#ifndef SOC_MEDIATEK_MT8196_SPI_H
-#define SOC_MEDIATEK_MT8196_SPI_H
+#ifndef __SOC_MEDIATEK_MT8196_SPI_H__
+#define __SOC_MEDIATEK_MT8196_SPI_H__

-#include <spi-generic.h>
+#include <soc/spi_common.h>
+
+#define SPI_BUS_NUMBER 8
+
+#define GET_SCK_REG(x) x->spi_cfg2_reg
+#define GET_TICK_DLY_REG(x) x->spi_cmd_reg
+
+DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
+DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
+DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 32, 16)
+DEFINE_BITFIELD(SPI_TICK_DLY, 24, 22)

/* Initialize SPI NOR Flash Controller */
 void mtk_snfc_init(void);
diff --git a/src/soc/mediatek/mt8196/spi.c b/src/soc/mediatek/mt8196/spi.c
index 770b5b0..f86253e 100644
--- a/src/soc/mediatek/mt8196/spi.c
+++ b/src/soc/mediatek/mt8196/spi.c
@@ -5,6 +5,8 @@
  * Chapter number: 13.9
  */

+#include <assert.h>
+#include <console/console.h>
 #include <device/mmio.h>
 #include <gpio.h>
 #include <soc/addressmap.h>
@@ -12,6 +14,92 @@
 #include <soc/spi.h>
 #include <spi_flash.h>

+struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
+	{
+		.regs = (void *)SPI0_BASE,
+		.cs_gpio = GPIO(SPI0_CSB),
+	},
+	{
+		.regs = (void *)SPI1_BASE,
+		.cs_gpio = GPIO(SPI1_CSB),
+	},
+	{
+		.regs = (void *)SPI2_BASE,
+		.cs_gpio = GPIO(EINT31),
+	},
+	{
+		.regs = (void *)SPI3_BASE,
+		.cs_gpio = GPIO(INT_SIM2),
+	},
+	{
+		.regs = (void *)SPI4_BASE,
+		.cs_gpio = GPIO(SPI_CSB_SEC),
+	},
+	{
+		.regs = (void *)SPI5_BASE,
+		.cs_gpio = GPIO(SPI5_CSB),
+	},
+	{
+		.regs = (void *)SPI6_BASE,
+		.cs_gpio = GPIO(I2SIN1_LRCK),
+	},
+	{
+		.regs = (void *)SPI7_BASE,
+		.cs_gpio = GPIO(EINT6),
+	},
+};
+
+static const struct pad_func pad_funcs[SPI_BUS_NUMBER][4] = {
+	{
+		PAD_FUNC_DOWN(SPI0_MI, SPI0_MI),
+		PAD_FUNC_GPIO(SPI0_CSB),
+		PAD_FUNC_DOWN(SPI0_MO, SPI0_MO),
+		PAD_FUNC_DOWN(SPI0_CLK, SPI0_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(SPI1_MI, SPI1_MI),
+		PAD_FUNC_GPIO(SPI1_CSB),
+		PAD_FUNC_DOWN(SPI1_MO, SPI1_MO),
+		PAD_FUNC_DOWN(SPI1_CLK, SPI1_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(EINT28, SPI2_A_MI),
+		PAD_FUNC_GPIO(EINT31),
+		PAD_FUNC_DOWN(EINT29, SPI2_A_MO),
+		PAD_FUNC_DOWN(EINT30, SPI2_A_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(EINT1, SPI3_A_MI),
+		PAD_FUNC_GPIO(INT_SIM2),
+		PAD_FUNC_DOWN(EINT0, SPI3_A_MO),
+		PAD_FUNC_DOWN(INT_SIM1, SPI3_A_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(SPI_MI_SEC, SPI4_A_MI),
+		PAD_FUNC_GPIO(SPI_CSB_SEC),
+		PAD_FUNC_DOWN(SPI_MO_SEC, SPI4_A_MO),
+		PAD_FUNC_DOWN(SPI_CLK_SEC, SPI4_A_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(SPI5_MI, SPI5_MI),
+		PAD_FUNC_GPIO(SPI5_CSB),
+		PAD_FUNC_DOWN(SPI5_MO, SPI5_MO),
+		PAD_FUNC_DOWN(SPI5_CLK, SPI5_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(I2SOUT1_DO, SPI6_A_MI),
+		PAD_FUNC_GPIO(I2SIN1_LRCK),
+		PAD_FUNC_DOWN(I2SIN1_DI, SPI6_A_MO),
+		PAD_FUNC_DOWN(I2SIN1_BCK, SPI6_A_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(EINT8, SPI7_A_MI),
+		PAD_FUNC_GPIO(EINT6),
+		PAD_FUNC_DOWN(EINT7, SPI7_A_MO),
+		PAD_FUNC_DOWN(EINT5, SPI7_A_CLK),
+	},
+};
+
 static const struct pad_func nor_pinmux[4] = {
    PAD_FUNC(SDA10, SF_CK, GPIO_PULL_DOWN),
    PAD_FUNC(SCL10, SF_CS, GPIO_PULL_UP),
@@ -25,6 +113,17 @@
    	mtk_snfc_init_pad_func(&nor_pinmux[i], GPIO_DRV_14_MA);
 }

+void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
+{
+	assert(bus < SPI_BUS_NUMBER);
+	const struct pad_func *ptr;
+
+	ptr = pad_funcs[bus];
+
+	for (unsigned int i = 0; i < SPI_BUS_NUMBER; i++)
+		gpio_set_mode(ptr[i].gpio, ptr[i].func);
+}
+
 static const struct spi_ctrlr spi_flash_ctrlr = {
    .max_xfer_size = 65535,
    .flash_probe = mtk_spi_flash_probe,
@@ -32,6 +131,11 @@

const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
    {
+		.ctrlr = &spi_ctrlr,
+		.bus_start = 0,
+		.bus_end = SPI_BUS_NUMBER - 1,
+	},
+	{
    	.ctrlr = &spi_flash_ctrlr,
    	.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
    	.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,