Change in coreboot[master]: google/cyan: fix FSP memory init params

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/22782

Change subject: google/cyan: fix FSP memory init params
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google/cyan: fix FSP memory init params

In the original Chromium source, PcdMemorySpdPtr is only set for
cyan, but none of the other Braswell variants. When upstreamed,
it was left set for all boards as it didn't appear to be problematic.
In wider testing, I came across one reks board for which it caused
FSP memory init to fail, so restricting the paramter to cyan only
as it was originally.

TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM,
observe board now successfully boots where it did not previously.

Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/cyan/romstage.c
1 file changed, 5 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22782/1

diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c
index c164ea4..5b4bcc0 100644
--- a/src/mainboard/google/cyan/romstage.c
+++ b/src/mainboard/google/cyan/romstage.c
@@ -33,11 +33,13 @@
    MEMORY_INIT_UPD *memory_params)
 {
    /* Update SPD data */
-	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN))
+	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
    	memory_params->PcdMemoryTypeEnable = MEM_DDR3;
-	else
+		memory_params->PcdMemorySpdPtr =
+				(u32)params->pei_data->spd_data_ch0;
+	} else
    	memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;
-	memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;
+
    memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;
    memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;