Patch set updated for coreboot: 9798527 northbridge/intel/pineview: Add minimal Pineview northbridge.
Damien Zammit (damien@zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10073
-gerrit
commit 97985274b777b870f2198211f212cd62b98a72d9 Author: Damien Zammit damien@zamaudio.com Date: Sun May 3 21:34:38 2015 +1000
northbridge/intel/pineview: Add minimal Pineview northbridge.
Based on i945. Tested on Intel D510MO mainboard.
Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit damien@zamaudio.com --- src/northbridge/intel/pineview/Kconfig | 73 ++++++ src/northbridge/intel/pineview/Makefile.inc | 31 +++ src/northbridge/intel/pineview/acpi.c | 76 ++++++ src/northbridge/intel/pineview/bootblock.c | 23 ++ src/northbridge/intel/pineview/pineview.h | 367 ++++++++++++++++++++++++++++ src/northbridge/intel/pineview/ram_calc.c | 62 +++++ src/northbridge/intel/pineview/udelay.c | 82 +++++++ 7 files changed, 714 insertions(+)
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig new file mode 100644 index 0000000..4d6dcc2 --- /dev/null +++ b/src/northbridge/intel/pineview/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_PINEVIEW + bool + +if NORTHBRIDGE_INTEL_PINEVIEW + +config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + #select HAVE_DEBUG_RAM_SETUP + select LAPIC_MONOTONIC_TIMER + select VGA + select PER_DEVICE_ACPI_TABLES + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/pineview/bootblock.c" + +config VGA_BIOS_ID + string + default "8086,a001" + +config CHANNEL_XOR_RANDOMIZATION + bool + default n + +config OVERRIDE_CLOCK_DISABLE + bool + default n + help + Usually system firmware turns off system memory clock + signals to unused SO-DIMM slots to reduce EMI and power + consumption. + However, some boards do not like unused clock signals to + be disabled. + +config MAXIMUM_SUPPORTED_FREQUENCY + int + default 0 + help + If non-zero, this designates the maximum DDR frequency + the board supports, despite what the chipset should be + capable of. + +config CHECK_SLFRCS_ON_RESUME + def_bool n + help + On some boards it may be neccessary to hard reset early + during resume from S3 if the SLFRCS register indicates that + a memory channel is not guaranteed to be in self-refresh. + On other boards the check always creates a false positive, + effectively making it impossible to resume. + +endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc new file mode 100644 index 0000000..657da33 --- /dev/null +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -0,0 +1,31 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += ram_calc.c +#ramstage-y += northbridge.c +#ramstage-y += gma.c +ramstage-y += acpi.c + +romstage-y += ram_calc.c +#romstage-y += raminit.c +#romstage-y += early_init.c +#romstage-y += errata.c +#romstage-y += debug.c + +smm-y += udelay.c diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c new file mode 100644 index 0000000..ae5fc37 --- /dev/null +++ b/src/northbridge/intel/pineview/acpi.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cbmem.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> +#include "pineview.h" + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 pciexbar_reg; + int max_buses; + + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + if (!dev) + return current; + + pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & (1 << 0))) + return current; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + max_buses = 256; + break; + case 1: // 128M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + max_buses = 128; + break; + case 2: // 64M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + max_buses = 64; + break; + default: // RSVD + return current; + } + + if (!pciexbar) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, max_buses - 1); + + return current; +} diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c new file mode 100644 index 0000000..badebea --- /dev/null +++ b/src/northbridge/intel/pineview/bootblock.c @@ -0,0 +1,23 @@ +#include <arch/io.h> + +#define PCIEXBAR 0x60 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h new file mode 100644 index 0000000..c4e0adc --- /dev/null +++ b/src/northbridge/intel/pineview/pineview.h @@ -0,0 +1,367 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H +#define NORTHBRIDGE_INTEL_PINEVIEW_H + +/* Northbridge BARs */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#include "../../../southbridge/intel/i82801gx/i82801gx.h" + +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ + +/* Display defines for the interrupt 15h handler */ +#define INT15_5F35_CL_DISPLAY_DEFAULT 0 +#define INT15_5F35_CL_DISPLAY_CRT (1 << 0) +#define INT15_5F35_CL_DISPLAY_TV (1 << 1) +#define INT15_5F35_CL_DISPLAY_EFP (1 << 2) +#define INT15_5F35_CL_DISPLAY_LCD (1 << 3) +#define INT15_5F35_CL_DISPLAY_CRT2 (1 << 4) +#define INT15_5F35_CL_DISPLAY_TV2 (1 << 5) +#define INT15_5F35_CL_DISPLAY_EFP2 (1 << 6) +#define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7) + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define GGC 0x52 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) +#define DEVEN_D2F0 (1 << 3) +#define DEVEN_D2F1 (1 << 4) + +#ifndef BOARD_DEVEN +#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) +#endif /* BOARD_DEVEN */ + +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 + +#define LAC 0x97 /* Legacy Access Control */ +#define TOLUD 0xb0 /* Top of Low Used Memory */ +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAM 0x9e /* Extended System Management RAM Control */ + +#define TOM 0xa0 + +#define SKPAD 0xdc /* Scratchpad Data */ + +/* Device 0:1.0 PCI configuration space (PCI Express) */ + +#define BCTRL1 0x3e /* 16bit */ +#define PEGSTS 0x214 /* 32bit */ + + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define GMADR 0x18 +#define GTTADR 0x1c +#define BSM 0x5c +#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ + + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +/* Chipset Control Registers */ +#define FSBPMC3 0x40 /* 32bit */ +#define FSBPMC4 0x44 /* 32bit */ +#define FSBSNPCTL 0x48 /* 32bit */ +#define SLPCTL 0x90 /* 32bit */ + +#define C0DRB0 0x200 /* 8bit */ +#define C0DRB1 0x202 /* 8bit */ +#define C0DRB2 0x204 /* 8bit */ +#define C0DRB3 0x206 /* 8bit */ +#define C0DRA0 0x208 /* 8bit */ +#define C0DRA2 0x20a /* 8bit */ + +#define C0DCLKDIS 0x10c /* 8bit */ +#define C0BNKARC 0x10e /* 16bit */ +#define C0DRT0 0x110 /* 32bit */ +#define C0DRT1 0x114 /* 32bit */ +#define C0DRT2 0x118 /* 32bit */ +#define C0DRT3 0x11c /* 32bit */ +#define C0DRC0 0x120 /* 32bit */ +#define C0DRC1 0x124 /* 32bit */ +#define C0DRC2 0x128 /* 32bit */ +#define C0AIT 0x130 /* 64bit */ +#define C0DCCFT 0x138 /* 64bit */ +#define C0GTEW 0x2a0 /* 32bit */ +#define C0GTC 0x2a4 /* 32bit */ +#define C0DTPEW 0x2a8 /* 64bit */ +#define C0DTAEW 0x2ac /* 64bit */ +#define C0DTC 0x158 /* 32bit */ +#define C0DMC 0x164 /* 32bit */ +#define C0ODT 0x298 /* 64bit */ + +#define C1DRB0 0x180 /* 8bit */ +#define C1DRB1 0x181 /* 8bit */ +#define C1DRB2 0x182 /* 8bit */ +#define C1DRB3 0x183 /* 8bit */ +#define C1DRA0 0x188 /* 8bit */ +#define C1DRA2 0x189 /* 8bit */ +#define C1DCLKDIS 0x18c /* 8bit */ +#define C1BNKARC 0x18e /* 16bit */ +#define C1DRT0 0x190 /* 32bit */ +#define C1DRT1 0x194 /* 32bit */ +#define C1DRT2 0x198 /* 32bit */ +#define C1DRT3 0x19c /* 32bit */ +#define C1DRC0 0x1a0 /* 32bit */ +#define C1DRC1 0x1a4 /* 32bit */ +#define C1DRC2 0x1a8 /* 32bit */ +#define C1AIT 0x1b0 /* 64bit */ +#define C1DCCFT 0x1b8 /* 64bit */ +#define C1GTEW 0x1c0 /* 32bit */ +#define C1GTC 0x1c4 /* 32bit */ +#define C1DTPEW 0x1c8 /* 64bit */ +#define C1DTAEW 0x1d0 /* 64bit */ +#define C1DTC 0x1d8 /* 32bit */ +#define C1DMC 0x1e4 /* 32bit */ +#define C1ODT 0x1e8 /* 64bit */ + +#define DCC 0x200 /* 32bit */ +#define CCCFT 0x208 /* 64bit */ +#define WCC 0x218 /* 32bit */ +#define MMARB0 0x220 /* 32bit */ +#define MMARB1 0x224 /* 32bit */ +#define SBTEST 0x230 /* 32bit */ +#define SBOCC 0x238 /* 32bit */ +#define ODTC 0x284 /* 32bit */ +#define SMVREFC 0x2a0 /* 32bit */ +#define DRTST 0x2a8 /* 32bit */ +#define REPC 0x2e0 /* 32bit */ +#define DQSMT 0x2f4 /* 16bit */ +#define RCVENMT 0x2f8 /* 32bit */ + +#define C0R0B00DQST 0x300 /* 64bit */ + +#define C0WL0REOST 0x340 /* 8bit */ +#define C0WL1REOST 0x341 /* 8bit */ +#define C0WL2REOST 0x342 /* 8bit */ +#define C0WL3REOST 0x343 /* 8bit */ +#define WDLLBYPMODE 0x360 /* 16bit */ +#define C0WDLLCMC 0x36c /* 32bit */ +#define C0HCTC 0x37c /* 8bit */ + +#define C1R0B00DQST 0x380 /* 64bit */ + +#define C1WL0REOST 0x3c0 /* 8bit */ +#define C1WL1REOST 0x3c1 /* 8bit */ +#define C1WL2REOST 0x3c2 /* 8bit */ +#define C1WL3REOST 0x3c3 /* 8bit */ +#define C1WDLLCMC 0x3ec /* 32bit */ +#define C1HCTC 0x3fc /* 8bit */ + +#define GBRCOMPCTL 0x400 /* 32bit */ + +#define SMSRCTL 0x408 /* XXX who knows */ +#define C0DRAMW 0x40c /* 16bit */ +#define G1SC 0x410 /* 8bit */ +#define G2SC 0x418 /* 8bit */ +#define G3SC 0x420 /* 8bit */ +#define G4SC 0x428 /* 8bit */ +#define G5SC 0x430 /* 8bit */ +#define G6SC 0x438 /* 8bit */ + +#define C1DRAMW 0x48c /* 16bit */ +#define G7SC 0x490 /* 8bit */ +#define G8SC 0x498 /* 8bit */ + +#define G1SRPUT 0x500 /* 256bit */ +#define G1SRPDT 0x520 /* 256bit */ +#define G2SRPUT 0x540 /* 256bit */ +#define G2SRPDT 0x560 /* 256bit */ +#define G3SRPUT 0x580 /* 256bit */ +#define G3SRPDT 0x5a0 /* 256bit */ +#define G4SRPUT 0x5c0 /* 256bit */ +#define G4SRPDT 0x5e0 /* 256bit */ +#define G5SRPUT 0x600 /* 256bit */ +#define G5SRPDT 0x620 /* 256bit */ +#define G6SRPUT 0x640 /* 256bit */ +#define G6SRPDT 0x660 /* 256bit */ +#define G7SRPUT 0x680 /* 256bit */ +#define G7SRPDT 0x6a0 /* 256bit */ +#define G8SRPUT 0x6c0 /* 256bit */ +#define G8SRPDT 0x6e0 /* 256bit */ + +/* Clock Controls */ +#define CLKCFG 0xc00 /* 32bit */ +#define UPMC1 0xc14 /* 16bit */ +#define CPCTL 0xc16 /* 16bit */ +#define SSKPD 0xc1c /* 16bit (scratchpad) */ +#define UPMC2 0xc20 /* 16bit */ +#define UPMC4 0xc30 /* 32bit */ +#define PLLMON 0xc34 /* 32bit */ +#define HGIPMC2 0xc38 /* 32bit */ + +/* Thermal Management Controls */ +#define TSC1 0xc88 /* 8bit */ +#define TSS1 0xc8a /* 8bit */ +#define TR1 0xc8b /* 8bit */ +#define TSTTP1 0xc8c /* 32bit */ +#define TCO1 0xc92 /* 8bit */ +#define THERM1_1 0xc94 /* 8bit */ +#define TCOF1 0xc96 /* 8bit */ +#define TIS1 0xc9a /* 16bit */ +#define TSTTP1_2 0xc9c /* 32bit */ +#define IUB 0xcd0 /* 32bit */ +#define TSC0_1 0xcd8 /* 8bit */ +#define TSS0 0xcda /* 8bit */ +#define TR0 0xcdb /* 8bit */ +#define TSTTP0_1 0xcdc /* 32bit */ +#define TCO0 0xce2 /* 8bit */ +#define THERM0_1 0xce4 /* 8bit */ +#define TCOF0 0xce6 /* 8bit */ +#define TIS0 0xcea /* 16bit */ +#define TSTTP0_2 0xcec /* 32bit */ +#define TERRCMD 0xcf0 /* 8bit */ +#define TSMICMD 0xcf1 /* 8bit */ +#define TSCICMD 0xcf2 /* 8bit */ +#define TINTRCMD 0xcf3 /* 8bit */ +#define EXTTSCS 0xcff /* 8bit */ +#define DFT_STRAP1 0xe08 /* 32bit */ + +/* ACPI Power Management Controls */ + +#define MIPMC3 0xbd8 /* 32bit */ + +#define C2C3TT 0xf00 /* 32bit */ +#define C3C4TT 0xf04 /* 32bit */ + +#define MIPMC4 0xf08 /* 16bit */ +#define MIPMC5 0xf0a /* 16bit */ +#define MIPMC6 0xf0c /* 16bit */ +#define MIPMC7 0xf0e /* 16bit */ +#define PMCFG 0xf10 /* 32bit */ +#define SLFRCS 0xf14 /* 32bit */ +#define GIPMC1 0xfb0 /* 32bit */ +#define FSBPMC1 0xfb8 /* 32bit */ +#define UPMC3 0xfc0 /* 32bit */ +#define ECO 0xffc /* 32bit */ + +/* + * EPBAR - Egress Port Root Complex Register Block + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define PORTARB 0x100 /* 256bit */ + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIPVCCAP2 0x008 /* 32bit */ + +#define DMIPVCCCTL 0x00c /* 16bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL0 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMICTL1 0x0f0 /* 32bit */ +#define DMICTL2 0x0fc /* 32bit */ + +#define DMICC 0x208 /* 32bit */ + +#define DMIDRCCFG 0xeb4 /* 32bit */ + +static inline void barrier(void) { asm("" ::: "memory"); } + +int i945_silicon_revision(void); +void i945_early_initialization(void); +void i945_late_initialization(int s3resume); + +/* provided by mainboard code */ +void setup_ich7_gpios(void); + +/* debugging functions */ +void print_pci_devices(void); +void dump_pci_device(unsigned dev); +void dump_pci_devices(void); +void dump_spd_registers(void); +void dump_mem(unsigned start, unsigned end); + +#endif /* __ACPI__ */ + +#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */ diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c new file mode 100644 index 0000000..6f19c1e --- /dev/null +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "pineview.h" + +static unsigned long find_ramtop(void) +{ + u32 tom; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), BSM); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x100000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x200000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x800000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long) tom; +} + +void *cbmem_top(void) +{ + return (void *) find_ramtop(); +} diff --git a/src/northbridge/intel/pineview/udelay.c b/src/northbridge/intel/pineview/udelay.c new file mode 100644 index 0000000..60ca9fb --- /dev/null +++ b/src/northbridge/intel/pineview/udelay.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> + +/** + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; /* ticks per us */ + + msr = rdmsr(MSR_FSB_FREQ); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + + multiply_to_tsc(&tscd, us, d); + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}
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Damien Zammit