Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36570 )
Change subject: soc/intel/common: pmclib: make use of the new ETR address API
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block/...
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block/...
PS4, Line 432: void pmc_global_reset_lock(void)
: {
: uint32_t *etr = soc_read_pmc_etr_addr();
: uint32_t reg;
:
: reg = read32(etr);
: reg = (reg & ~CF9_GLB_RST) | CF9_LOCK;
: write32(etr, reg);
: }
Well, I just wanted to continue your idea of moving this back to soc/ (which I definitely don't pref […]
I was responding to Arthur, but gerrit won't let me quote old comments. Sorry for not being clearer. I was explaining (and your other CL brings it to attention) the dependencies and the combinations needed to support as well as open coding everything which Arthur suggested. That's what triggered this CL to begin with because of noisiness and implicit dependencies.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d
Gerrit-Change-Number: 36570
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